?? at91sam9260.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9260.h
// Object : AT91SAM9260 definitions
// Generated : AT91 SW Application Group 10/13/2005 (14:44:43)
//
// CVS Reference : /AT91SAM9260.pl/1.9/Fri Sep 30 11:52:03 2005//
// CVS Reference : /SYS_SAM9260.pl/1.2/Fri Sep 30 11:57:05 2005//
// CVS Reference : /HMATRIX1_SAM9260.pl/1.2/Thu Oct 13 11:34:36 2005//
// CVS Reference : /CCR_SAM9260.pl/1.1/Fri Sep 30 11:55:31 2005//
// CVS Reference : /PMC_SAM9260.pl/1.2/Thu Oct 13 08:55:48 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 09 10:52:25 2004//
// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 03 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 03 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 04 13:57:00 2004//
// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 06 14:16:58 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 04 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 04 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 04 13:58:52 2004//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 09 16:31:51 2005//
// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 03 13:20:23 2005//
// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
// CVS Reference : /UDP_6083C.pl/1.2/Tue May 10 12:40:17 2005//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 09 07:05:57 2005//
// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 07:53:33 2005//
// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 09 17:16:57 2005//
// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 03 11:11:48 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYS {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
AT91_REG Reserved0[118]; //
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
AT91_REG Reserved1[96]; //
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5
AT91_REG Reserved2[10]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
AT91_REG Reserved3[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0
AT91_REG Reserved4[1]; //
AT91_REG MATRIX_PRAS1; // PRAS1
AT91_REG Reserved5[1]; //
AT91_REG MATRIX_PRAS2; // PRAS2
AT91_REG Reserved6[1]; //
AT91_REG MATRIX_PRAS3; // PRAS3
AT91_REG Reserved7[1]; //
AT91_REG MATRIX_PRAS4; // PRAS4
AT91_REG Reserved8[23]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved9[6]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved10[55]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved11[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved12[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved13[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved14[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved15[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved16[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOA_OER; // Output Enable Register
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