# ----------------------------------------------------------------------------
#          ATMEL Microcontroller Software Support  -  ROUSSET  -
# ----------------------------------------------------------------------------
#  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
#  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
#  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
#  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
#  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
#  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
#  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
#  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# ----------------------------------------------------------------------------
# File Name           : AT91SAM9260.h
# Object              : AT91SAM9260 definitions
# Generated           : AT91 SW Application Group  10/13/2005 (14:44:46)
# 
# CVS Reference       : /AT91SAM9260.pl/1.9/Fri Sep 30 11:52:03 2005//
# CVS Reference       : /SYS_SAM9260.pl/1.2/Fri Sep 30 11:57:05 2005//
# CVS Reference       : /HMATRIX1_SAM9260.pl/1.2/Thu Oct 13 11:34:36 2005//
# CVS Reference       : /CCR_SAM9260.pl/1.1/Fri Sep 30 11:55:31 2005//
# CVS Reference       : /PMC_SAM9260.pl/1.2/Thu Oct 13 08:55:48 2005//
# CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
# CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug 09 10:52:25 2004//
# CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
# CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
# CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb 03 09:02:11 2005//
# CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
# CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb 03 10:29:42 2005//
# CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov 04 13:57:00 2004//
# CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct 06 14:16:58 2004//
# CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov 04 13:57:22 2004//
# CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov 04 13:56:22 2004//
# CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov 04 13:58:52 2004//
# CVS Reference       : /TC_6082A.pl/1.7/Wed Mar 09 16:31:51 2005//
# CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun 03 13:20:23 2005//
# CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
# CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
# CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
# CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
# CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
# CVS Reference       : /UDP_6083C.pl/1.2/Tue May 10 12:40:17 2005//
# CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
# CVS Reference       : /TBOX_XXXX.pl/1.15/Thu Jun 09 07:05:57 2005//
# CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 07:53:33 2005//
# CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb 09 17:16:57 2005//
# CVS Reference       : /ISI_xxxxx.pl/1.3/Thu Mar 03 11:11:48 2005//
# ----------------------------------------------------------------------------

rdf.version=1

~sysinclude=arm_default.rdf
~sysinclude=arm_status.rdf
# ========== Register definition for SYS peripheral ========== 
AT91C_SYS_GPBR3.name="AT91C_SYS_GPBR3"
AT91C_SYS_GPBR3.description="General Purpose Register 3"
AT91C_SYS_GPBR3.helpkey="General Purpose Register 3"
AT91C_SYS_GPBR3.access=memorymapped
AT91C_SYS_GPBR3.address=0xFFFFFFFF
AT91C_SYS_GPBR3.width=32
AT91C_SYS_GPBR3.byteEndian=little
AT91C_SYS_GPBR1.name="AT91C_SYS_GPBR1"
AT91C_SYS_GPBR1.description="General Purpose Register 1"
AT91C_SYS_GPBR1.helpkey="General Purpose Register 1"
AT91C_SYS_GPBR1.access=memorymapped
AT91C_SYS_GPBR1.address=0xFFFFFFFF
AT91C_SYS_GPBR1.width=32
AT91C_SYS_GPBR1.byteEndian=little
AT91C_SYS_GPBR2.name="AT91C_SYS_GPBR2"
AT91C_SYS_GPBR2.description="General Purpose Register 2"
AT91C_SYS_GPBR2.helpkey="General Purpose Register 2"
AT91C_SYS_GPBR2.access=memorymapped
AT91C_SYS_GPBR2.address=0xFFFFFFFF
AT91C_SYS_GPBR2.width=32
AT91C_SYS_GPBR2.byteEndian=little
AT91C_SYS_GPBR0.name="AT91C_SYS_GPBR0"
AT91C_SYS_GPBR0.description="General Purpose Register 0"
AT91C_SYS_GPBR0.helpkey="General Purpose Register 0"
AT91C_SYS_GPBR0.access=memorymapped
AT91C_SYS_GPBR0.address=0xFFFFFFFF
AT91C_SYS_GPBR0.width=32
AT91C_SYS_GPBR0.byteEndian=little
# ========== Register definition for EBI peripheral ========== 
AT91C_EBI_DUMMY.name="AT91C_EBI_DUMMY"
AT91C_EBI_DUMMY.description="Dummy register - Do not use"
AT91C_EBI_DUMMY.helpkey="Dummy register - Do not use"
AT91C_EBI_DUMMY.access=memorymapped
AT91C_EBI_DUMMY.address=0xFFFFEA00
AT91C_EBI_DUMMY.width=32
AT91C_EBI_DUMMY.byteEndian=little
# ========== Register definition for HECC peripheral ========== 
AT91C_HECC_PR.name="AT91C_HECC_PR"
AT91C_HECC_PR.description=" ECC Parity register"
AT91C_HECC_PR.helpkey=" ECC Parity register"
AT91C_HECC_PR.access=memorymapped
AT91C_HECC_PR.address=0xFFFFE80C
AT91C_HECC_PR.width=32
AT91C_HECC_PR.byteEndian=little
AT91C_HECC_PR.permission.write=none
AT91C_HECC_MR.name="AT91C_HECC_MR"
AT91C_HECC_MR.description=" ECC Page size register"
AT91C_HECC_MR.helpkey=" ECC Page size register"
AT91C_HECC_MR.access=memorymapped
AT91C_HECC_MR.address=0xFFFFE804
AT91C_HECC_MR.width=32
AT91C_HECC_MR.byteEndian=little
AT91C_HECC_NPR.name="AT91C_HECC_NPR"
AT91C_HECC_NPR.description=" ECC Parity N register"
AT91C_HECC_NPR.helpkey=" ECC Parity N register"
AT91C_HECC_NPR.access=memorymapped
AT91C_HECC_NPR.address=0xFFFFE810
AT91C_HECC_NPR.width=32
AT91C_HECC_NPR.byteEndian=little
AT91C_HECC_NPR.permission.write=none
AT91C_HECC_SR.name="AT91C_HECC_SR"
AT91C_HECC_SR.description=" ECC Status register"
AT91C_HECC_SR.helpkey=" ECC Status register"
AT91C_HECC_SR.access=memorymapped
AT91C_HECC_SR.address=0xFFFFE808
AT91C_HECC_SR.width=32
AT91C_HECC_SR.byteEndian=little
AT91C_HECC_SR.permission.write=none
AT91C_HECC_CR.name="AT91C_HECC_CR"
AT91C_HECC_CR.description=" ECC reset register"
AT91C_HECC_CR.helpkey=" ECC reset register"
AT91C_HECC_CR.access=memorymapped
AT91C_HECC_CR.address=0xFFFFE800
AT91C_HECC_CR.width=32
AT91C_HECC_CR.byteEndian=little
AT91C_HECC_CR.type=enum
AT91C_HECC_CR.enum.0.name=*** Write only ***
AT91C_HECC_CR.enum.1.name=Error
AT91C_HECC_VR.name="AT91C_HECC_VR"
AT91C_HECC_VR.description=" ECC Version register"
AT91C_HECC_VR.helpkey=" ECC Version register"
AT91C_HECC_VR.access=memorymapped
AT91C_HECC_VR.address=0xFFFFE8FC
AT91C_HECC_VR.width=32
AT91C_HECC_VR.byteEndian=little
AT91C_HECC_VR.permission.write=none
# ========== Register definition for SDRAMC peripheral ========== 
AT91C_SDRAMC_ISR.name="AT91C_SDRAMC_ISR"
AT91C_SDRAMC_ISR.description="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_ISR.helpkey="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_ISR.access=memorymapped
AT91C_SDRAMC_ISR.address=0xFFFFEA20
AT91C_SDRAMC_ISR.width=32
AT91C_SDRAMC_ISR.byteEndian=little
AT91C_SDRAMC_ISR.permission.write=none
AT91C_SDRAMC_IDR.name="AT91C_SDRAMC_IDR"
AT91C_SDRAMC_IDR.description="SDRAM Controller Interrupt Disable Register"
AT91C_SDRAMC_IDR.helpkey="SDRAM Controller Interrupt Disable Register"
AT91C_SDRAMC_IDR.access=memorymapped
AT91C_SDRAMC_IDR.address=0xFFFFEA18
AT91C_SDRAMC_IDR.width=32
AT91C_SDRAMC_IDR.byteEndian=little
AT91C_SDRAMC_IDR.type=enum
AT91C_SDRAMC_IDR.enum.0.name=*** Write only ***
AT91C_SDRAMC_IDR.enum.1.name=Error
AT91C_SDRAMC_MR.name="AT91C_SDRAMC_MR"
AT91C_SDRAMC_MR.description="SDRAM Controller Mode Register"
AT91C_SDRAMC_MR.helpkey="SDRAM Controller Mode Register"
AT91C_SDRAMC_MR.access=memorymapped
AT91C_SDRAMC_MR.address=0xFFFFEA00
AT91C_SDRAMC_MR.width=32
AT91C_SDRAMC_MR.byteEndian=little
AT91C_SDRAMC_CR.name="AT91C_SDRAMC_CR"
AT91C_SDRAMC_CR.description="SDRAM Controller Configuration Register"
AT91C_SDRAMC_CR.helpkey="SDRAM Controller Configuration Register"
AT91C_SDRAMC_CR.access=memorymapped
AT91C_SDRAMC_CR.address=0xFFFFEA08
AT91C_SDRAMC_CR.width=32
AT91C_SDRAMC_CR.byteEndian=little
AT91C_SDRAMC_LPR.name="AT91C_SDRAMC_LPR"
AT91C_SDRAMC_LPR.description="SDRAM Controller Low Power Register"
AT91C_SDRAMC_LPR.helpkey="SDRAM Controller Low Power Register"
AT91C_SDRAMC_LPR.access=memorymapped
AT91C_SDRAMC_LPR.address=0xFFFFEA10
AT91C_SDRAMC_LPR.width=32
AT91C_SDRAMC_LPR.byteEndian=little
AT91C_SDRAMC_MDR.name="AT91C_SDRAMC_MDR"
AT91C_SDRAMC_MDR.description="SDRAM Memory Device Register"
AT91C_SDRAMC_MDR.helpkey="SDRAM Memory Device Register"
AT91C_SDRAMC_MDR.access=memorymapped
AT91C_SDRAMC_MDR.address=0xFFFFEA24
AT91C_SDRAMC_MDR.width=32
AT91C_SDRAMC_MDR.byteEndian=little
AT91C_SDRAMC_MDR.permission.write=none
AT91C_SDRAMC_TR.name="AT91C_SDRAMC_TR"
AT91C_SDRAMC_TR.description="SDRAM Controller Refresh Timer Register"
AT91C_SDRAMC_TR.helpkey="SDRAM Controller Refresh Timer Register"
AT91C_SDRAMC_TR.access=memorymapped
AT91C_SDRAMC_TR.address=0xFFFFEA04
AT91C_SDRAMC_TR.width=32
AT91C_SDRAMC_TR.byteEndian=little
AT91C_SDRAMC_HSR.name="AT91C_SDRAMC_HSR"
AT91C_SDRAMC_HSR.description="SDRAM Controller High Speed Register"
AT91C_SDRAMC_HSR.helpkey="SDRAM Controller High Speed Register"
AT91C_SDRAMC_HSR.access=memorymapped
AT91C_SDRAMC_HSR.address=0xFFFFEA0C
AT91C_SDRAMC_HSR.width=32
AT91C_SDRAMC_HSR.byteEndian=little
AT91C_SDRAMC_IER.name="AT91C_SDRAMC_IER"
AT91C_SDRAMC_IER.description="SDRAM Controller Interrupt Enable Register"
AT91C_SDRAMC_IER.helpkey="SDRAM Controller Interrupt Enable Register"
AT91C_SDRAMC_IER.access=memorymapped
AT91C_SDRAMC_IER.address=0xFFFFEA14
AT91C_SDRAMC_IER.width=32
AT91C_SDRAMC_IER.byteEndian=little
AT91C_SDRAMC_IER.type=enum
AT91C_SDRAMC_IER.enum.0.name=*** Write only ***
AT91C_SDRAMC_IER.enum.1.name=Error
AT91C_SDRAMC_IMR.name="AT91C_SDRAMC_IMR"
AT91C_SDRAMC_IMR.description="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_IMR.helpkey="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_IMR.access=memorymapped
AT91C_SDRAMC_IMR.address=0xFFFFEA1C
AT91C_SDRAMC_IMR.width=32
AT91C_SDRAMC_IMR.byteEndian=little
AT91C_SDRAMC_IMR.permission.write=none
# ========== Register definition for SMC peripheral ========== 
AT91C_SMC_CYCLE1.name="AT91C_SMC_CYCLE1"
AT91C_SMC_CYCLE1.description=" Cycle Register for CS 1"
AT91C_SMC_CYCLE1.helpkey=" Cycle Register for CS 1"
AT91C_SMC_CYCLE1.access=memorymapped
AT91C_SMC_CYCLE1.address=0xFFFFEC18
AT91C_SMC_CYCLE1.width=32
AT91C_SMC_CYCLE1.byteEndian=little
AT91C_SMC_CTRL7.name="AT91C_SMC_CTRL7"
AT91C_SMC_CTRL7.description=" Control Register for CS 7"
AT91C_SMC_CTRL7.helpkey=" Control Register for CS 7"
AT91C_SMC_CTRL7.access=memorymapped
AT91C_SMC_CTRL7.address=0xFFFFEC7C
AT91C_SMC_CTRL7.width=32
AT91C_SMC_CTRL7.byteEndian=little
AT91C_SMC_CTRL2.name="AT91C_SMC_CTRL2"
AT91C_SMC_CTRL2.description=" Control Register for CS 2"
AT91C_SMC_CTRL2.helpkey=" Control Register for CS 2"
AT91C_SMC_CTRL2.access=memorymapped
AT91C_SMC_CTRL2.address=0xFFFFEC2C
AT91C_SMC_CTRL2.width=32
AT91C_SMC_CTRL2.byteEndian=little
AT91C_SMC_PULSE2.name="AT91C_SMC_PULSE2"
AT91C_SMC_PULSE2.description=" Pulse Register for CS 2"
AT91C_SMC_PULSE2.helpkey=" Pulse Register for CS 2"
AT91C_SMC_PULSE2.access=memorymapped
AT91C_SMC_PULSE2.address=0xFFFFEC24
AT91C_SMC_PULSE2.width=32
AT91C_SMC_PULSE2.byteEndian=little
AT91C_SMC_CTRL1.name="AT91C_SMC_CTRL1"
AT91C_SMC_CTRL1.description=" Control Register for CS 1"
AT91C_SMC_CTRL1.helpkey=" Control Register for CS 1"
AT91C_SMC_CTRL1.access=memorymapped
AT91C_SMC_CTRL1.address=0xFFFFEC1C
AT91C_SMC_CTRL1.width=32
AT91C_SMC_CTRL1.byteEndian=little
AT91C_SMC_SETUP4.name="AT91C_SMC_SETUP4"
AT91C_SMC_SETUP4.description=" Setup Register for CS 4"
AT91C_SMC_SETUP4.helpkey=" Setup Register for CS 4"
AT91C_SMC_SETUP4.access=memorymapped
AT91C_SMC_SETUP4.address=0xFFFFEC40
AT91C_SMC_SETUP4.width=32
AT91C_SMC_SETUP4.byteEndian=little
AT91C_SMC_CYCLE3.name="AT91C_SMC_CYCLE3"
AT91C_SMC_CYCLE3.description=" Cycle Register for CS 3"
AT91C_SMC_CYCLE3.helpkey=" Cycle Register for CS 3"
AT91C_SMC_CYCLE3.access=memorymapped
AT91C_SMC_CYCLE3.address=0xFFFFEC38
AT91C_SMC_CYCLE3.width=32
AT91C_SMC_CYCLE3.byteEndian=little
AT91C_SMC_SETUP3.name="AT91C_SMC_SETUP3"
AT91C_SMC_SETUP3.description=" Setup Register for CS 3"
AT91C_SMC_SETUP3.helpkey=" Setup Register for CS 3"
AT91C_SMC_SETUP3.access=memorymapped
AT91C_SMC_SETUP3.address=0xFFFFEC30
AT91C_SMC_SETUP3.width=32
AT91C_SMC_SETUP3.byteEndian=little
AT91C_SMC_CYCLE2.name="AT91C_SMC_CYCLE2"
AT91C_SMC_CYCLE2.description=" Cycle Register for CS 2"
AT91C_SMC_CYCLE2.helpkey=" Cycle Register for CS 2"
AT91C_SMC_CYCLE2.access=memorymapped
AT91C_SMC_CYCLE2.address=0xFFFFEC28
AT91C_SMC_CYCLE2.width=32
AT91C_SMC_CYCLE2.byteEndian=little
AT91C_SMC_SETUP2.name="AT91C_SMC_SETUP2"
AT91C_SMC_SETUP2.description=" Setup Register for CS 2"
AT91C_SMC_SETUP2.helpkey=" Setup Register for CS 2"
AT91C_SMC_SETUP2.access=memorymapped
AT91C_SMC_SETUP2.address=0xFFFFEC20
AT91C_SMC_SETUP2.width=32
AT91C_SMC_SETUP2.byteEndian=little
AT91C_SMC_PULSE5.name="AT91C_SMC_PULSE5"
AT91C_SMC_PULSE5.description=" Pulse Register for CS 5"
AT91C_SMC_PULSE5.helpkey=" Pulse Register for CS 5"
AT91C_SMC_PULSE5.access=memorymapped
AT91C_SMC_PULSE5.address=0xFFFFEC54
AT91C_SMC_PULSE5.width=32
AT91C_SMC_PULSE5.byteEndian=little
AT91C_SMC_CTRL4.name="AT91C_SMC_CTRL4"
AT91C_SMC_CTRL4.description=" Control Register for CS 4"
AT91C_SMC_CTRL4.helpkey=" Control Register for CS 4"
AT91C_SMC_CTRL4.access=memorymapped
AT91C_SMC_CTRL4.address=0xFFFFEC4C
AT91C_SMC_CTRL4.width=32
AT91C_SMC_CTRL4.byteEndian=little
AT91C_SMC_PULSE4.name="AT91C_SMC_PULSE4"
AT91C_SMC_PULSE4.description=" Pulse Register for CS 4"
AT91C_SMC_PULSE4.helpkey=" Pulse Register for CS 4"
AT91C_SMC_PULSE4.access=memorymapped
AT91C_SMC_PULSE4.address=0xFFFFEC44
AT91C_SMC_PULSE4.width=32
AT91C_SMC_PULSE4.byteEndian=little
AT91C_SMC_CTRL3.name="AT91C_SMC_CTRL3"
AT91C_SMC_CTRL3.description=" Control Register for CS 3"
AT91C_SMC_CTRL3.helpkey=" Control Register for CS 3"
AT91C_SMC_CTRL3.access=memorymapped
AT91C_SMC_CTRL3.address=0xFFFFEC3C