library ieee;
use ieee.std_logic_1164.all;

entity dpll is
   port (clk_original: in std_logic;
         reset:  in std_logic;
         data: in std_logic;
         clk_extracted: out std_logic;
         clk_extracted2: out std_logic
         --test : out std_logic_vector(1 downto 0 )
         );
end dpll;

architecture arc_dpll of dpll is
   
     component detector
         port ( clk_f0: in std_logic;
           --clk_2f0: in std_logic;
           reset:     in std_logic;
           data: in std_logic;
           fast: out std_logic;
           slow: out std_logic);
     end component;
     
     component filter
      port (clk: in std_logic;
           reset:  in std_logic;
           slow: in std_logic;
           fast: in std_logic;
           decr: out std_logic;
           incr: out std_logic);
    end component;
     
     component dco
        port(clk: in std_logic;
          reset:  in std_logic;
          decr: in std_logic;
          incr: in std_logic;
          clk_2f0: out std_logic;
          clk_f0: out std_logic);
     end component;
     
     signal clk_2f0: std_logic;
     signal clk_f0: std_logic;
     signal clk_lock: std_logic;
     signal fast: std_logic;
     signal slow: std_logic;
     signal decr: std_logic;
     signal incr: std_logic;
     signal clk_high: std_logic;
     
     begin
     
        u_detector: detector
            port map(clk_2f0,  reset, data, fast, slow);
        u_filter:filter
            port map(clk_original, reset, slow, fast,decr, incr);
        u_dco:dco
            port map(clk_original, reset, decr, incr,clk_2f0,clk_f0);
        
     --  process
     --  begin
     --    wait until clk_original'event and clk_original='1';
     --      clk_lock<=clk_f0;
           clk_extracted<=clk_2f0; --clk_lock; 
           clk_extracted2<=clk_f0;
     --  end process;    
       
       --test<=decr&incr&data&clk_f0;
           
  end arc_dpll;