/**********************************************************************
* File: EPwm.c
* Devices: TMS320F2808, TMS320F2806, TMS320F2801
* Author: David M. Alter, Texas Instruments Inc.
* History:
*   02/11/05 - original (D. Alter)
**********************************************************************/

#include "DSP280x_Device.h"

// EXAMPLE_BIOS or EXAMPLE_NONBIOS are defined in the CCS project build options
#ifdef EXAMPLE_BIOS
    #include "example_BIOS.h"
#endif

#ifdef EXAMPLE_NONBIOS
    #include "example_nonBIOS.h"
#endif


/*** Constants ***/
#define ADC_sample_period   1999			// 1999 = 50KHz sampling w/ 100MHz CPUCLK
#define PWM_half_period    25000			// period/2 for 2kHz symmetric PWM
#define PWM_duty_cycle     18750			// 25% duty cycle


/**********************************************************************
* Function: InitEPwm()
*
* Description: Initializes the Enhanced PWM modules on the F280x.
**********************************************************************/
void InitEPwm(void)
{

/************************************************************/
/*** Must disable the clock to the ePWM modules if you    ***/
/*** want all ePMW modules synchronized.                  ***/
/************************************************************/
	asm(" EALLOW");						// Enable EALLOW protected register access
	SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	asm(" EDIS");						// Disable EALLOW protected register access


/************************************************************/
/*** Configure ePWM2 to trigger the ADC at a 50KHz rate   ***/
/************************************************************/

	EPwm2Regs.TBCTL.bit.CTRMODE = 0x3;		// Disable the timer

	EPwm2Regs.TBCTL.all = 0xC033;			// Configure timer control register
/*
 bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
 bit 13        0:      PHSDIR, 0 = count down after sync event
 bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
 bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = SYSCLKOUT/1
 bit 6         0:      SWFSYNC, 0 = no software sync produced
 bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
 bit 3         0:      PRDLD, 0 = reload PRD on counter=0
 bit 2         0:      PHSEN, 0 = phase control disabled
 bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)
*/

	EPwm2Regs.TBCTR = 0x0000;				// Clear timer counter
	EPwm2Regs.TBPRD = ADC_sample_period;	// Set timer period
	EPwm2Regs.TBPHS.half.TBPHS = 0x0000;	// Set timer phase

	EPwm2Regs.ETPS.all = 0x0100;			// Configure SOCA
/*
 bit 15-14     00:     EPWMxSOCB, read-only
 bit 13-12     00:     SOCBPRD, don't care
 bit 11-10     00:     EPWMxSOCA, read-only
 bit 9-8       01:     SOCAPRD, 01 = generate SOCA on first event
 bit 7-4       0000:   reserved
 bit 3-2       00:     INTCNT, don't care
 bit 1-0       00:     INTPRD, don't care
*/

	EPwm2Regs.ETSEL.all = 0x0A00;			// Enable SOCA to ADC
/*
 bit 15        0:      SOCBEN, 0 = disable SOCB
 bit 14-12     000:    SOCBSEL, don't care
 bit 11        1:      SOCAEN, 1 = enable SOCA
 bit 10-8      010:    SOCASEL, 010 = SOCA on PRD event
 bit 7-4       0000:   reserved
 bit 3         0:      INTEN, 0 = disable interrupt
 bit 2-0       000:    INTSEL, don't care
*/

	EPwm2Regs.TBCTL.bit.CTRMODE = 0x0;		// Enable the timer in count up mode


/************************************************************/
/*** Configure ePWM1 for 2KHz symmetric PWM on EPWM1A pin ***/
/************************************************************/
	EPwm1Regs.TBCTL.bit.CTRMODE = 0x3;		// Disable the timer

	EPwm1Regs.TBCTL.all = 0xC033;			// Configure timer control register
/*
 bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
 bit 13        0:      PHSDIR, 0 = count down after sync event
 bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
 bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = SYSCLKOUT/1
 bit 6         0:      SWFSYNC, 0 = no software sync produced
 bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
 bit 3         0:      PRDLD, 0 = reload PRD on counter=0
 bit 2         0:      PHSEN, 0 = phase control disabled
 bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)
*/

	EPwm1Regs.TBCTR = 0x0000;				// Clear timer counter
	EPwm1Regs.TBPRD = PWM_half_period;		// Set timer period
	EPwm1Regs.TBPHS.half.TBPHS = 0x0000;	// Set timer phase

	EPwm1Regs.CMPA.half.CMPA = PWM_duty_cycle;	// Set PWM duty cycle

	EPwm1Regs.CMPCTL.all = 0x0002;			// Compare control register
/*
 bit 15-10     0's:    reserved
 bit 9         0:      SHDWBFULL, read-only
 bit 8         0:      SHDWAFULL, read-only
 bit 7         0:      reserved
 bit 6         0:      SHDWBMODE, don't care
 bit 5         0:      reserved
 bit 4         0:      SHDWAMODE, 0 = shadow mode
 bit 3-2       00:     LOADBMODE, don't care
 bit 1-0       10:     LOADAMODE, 10 = load on zero or PRD match
*/

	EPwm1Regs.AQCTLA.all = 0x0060;		// Action-qualifier control register A
/*
 bit 15-12     0000:   reserved
 bit 11-10     00:     CBD, 00 = do nothing
 bit 9-8       00:     CBU, 00 = do nothing
 bit 7-6       01:     CAD, 01 = clear
 bit 5-4       10:     CAU, 10 = set
 bit 3-2       00:     PRD, 00 = do nothing
 bit 1-0       00:     ZRO, 00 = do nothing
*/

	EPwm1Regs.AQSFRC.all = 0x0000;		// Action-qualifier s/w force register
/*
 bit 15-8      0's:    reserved
 bit 7-6       00:     RLDCSF, 00 = reload AQCSFRC on zero
 bit 5         0:      OTSFB, 0 = do not initiate a s/w forced event on output B
 bit 4-3       00:     ACTSFB, don't care
 bit 2         0:      OTSFA, 0 = do not initiate a s/w forced event on output A
 bit 1-0       00:     ACTSFA, don't care
*/

	EPwm1Regs.AQCSFRC.all = 0x0000;		// Action-qualifier continuous s/w force register
/*
 bit 15-4      0's:    reserved
 bit 3-2       00:     CSFB, 00 = forcing disabled
 bit 1-0       00:     CSFA, 00 = forcing disabled
*/

	EPwm1Regs.DBCTL.bit.OUT_MODE = 0;	// Deadband disabled
	EPwm1Regs.PCCTL.bit.CHPEN = 0;		// PWM chopper unit disabled
	EPwm1Regs.TZCTL.bit.TZA = 0x3;		// Trip action disabled for output A

	EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;	// Enable the timer in count up/down mode

} // end InitEPwm()


/*** end of file *****************************************************/