{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "gclk Global clock in PIN 28 " "Info: Automatically promoted signal \"gclk\" to use Global clock in PIN 28" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "RESETFPGA Global clock in PIN 153 " "Info: Automatically promoted some destinations of signal \"RESETFPGA\" to use Global clock in PIN 153" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifoef~4 " "Info: Destination \"fifoef~4\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fifoff~89 " "Info: Destination \"fifoff~89\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[0\]~reg0 " "Info: Destination \"FX2FD\[0\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "process1~0 " "Info: Destination \"process1~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[1\]~reg0 " "Info: Destination \"FX2FD\[1\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[2\]~reg0 " "Info: Destination \"FX2FD\[2\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[3\]~reg0 " "Info: Destination \"FX2FD\[3\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[4\]~reg0 " "Info: Destination \"FX2FD\[4\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[5\]~reg0 " "Info: Destination \"FX2FD\[5\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FX2FD\[6\]~reg0 " "Info: Destination \"FX2FD\[6\]~reg0\" may be non-global or may not use global clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 15 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}