{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.141 ns memory register " "Info: Estimated most critical path is memory to register delay of 6.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a2~portb_address_reg0 1 MEM M4K_X17_Y15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y15; Fanout = 1; MEM Node = 'altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a2~portb_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a2~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_lk81.tdf" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 108 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|q_b\[2\] 2 MEM M4K_X17_Y15 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y15; Fanout = 1; MEM Node = 'altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|q_b\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "4.317 ns" { altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a2~portb_address_reg0 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[2] } "NODE_NAME" } "" } } { "db/altsyncram_lk81.tdf" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.086 ns) + CELL(0.738 ns) 6.141 ns data2usb\[2\] 3 REG LAB_X16_Y16 1 " "Info: 3: + IC(1.086 ns) + CELL(0.738 ns) = 6.141 ns; Loc. = LAB_X16_Y16; Fanout = 1; REG Node = 'data2usb\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "1.824 ns" { altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[2] data2usb[2] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.055 ns ( 82.32 % ) " "Info: Total cell delay = 5.055 ns ( 82.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.086 ns ( 17.68 % ) " "Info: Total interconnect delay = 1.086 ns ( 17.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "6.141 ns" { altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a2~portb_address_reg0 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[2] data2usb[2] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 6 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 6%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}