{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "34 " "Warning: Following 34 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RDY2 GND " "Info: Pin RDY2 has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 33 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RDY2" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { RDY2 } "NODE_NAME" } "" } } { "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { RDY2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RDY3 GND " "Info: Pin RDY3 has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 34 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RDY3" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { RDY3 } "NODE_NAME" } "" } } { "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { RDY3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RDY4 GND " "Info: Pin RDY4 has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 35 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RDY4" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { RDY4 } "NODE_NAME" } "" } } { "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { RDY4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RDY5 GND " "Info: Pin RDY5 has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 36 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RDY5" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { RDY5 } "NODE_NAME" } "" } } { "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { RDY5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAMFD\[0\] GND " "Info: Pin SRAMFD\[0\] has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[0] } "NODE_NAME" } "" } } { "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAMFD\[1\] GND " "Info: Pin SRAMFD\[1\] has GND driving its datain port" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盤/CD1/測試程序源代碼/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盤/CD1/測試程序源代碼/GPIF_