#ifndef CYGONCE_SMDK2410_H
#define CYGONCE_SMDK2410_H

//=============================================================================
//
//      s3c2410x.h
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// for more details.
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//
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// or inline functions from this file, or you compile this file and link it
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//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    michael anburaj <michaelanburaj@hotmail.com>
// Contributors: michael anburaj <michaelanburaj@hotmail.com>
// Date:         2003-08-01
// Purpose:      SMDK2410 platform specific support definitions
// Description: 
// Usage:        #include <cyg/hal/s3c2410x.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal_arm_arm9_smdk2410.h>

// Memory layout details needed by conversion macro
#define SMDK2410_SDRAM_PHYS_BASE         0x30000000
#define SMDK2410_SDRAM_VIRT_BASE         0x00000000

#define SMDK2410_FLASH_PHYS_BASE         0x00000000
#define SMDK2410_FLASH_VIRT_BASE         0x80000000


// Internal clocks
#define FCLK CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK
#define HCLK CYGNUM_HAL_ARM_SMDK2410_BUS_CLOCK

#define PCLK CYGNUM_HAL_ARM_SMDK2410_PERIPHERAL_CLOCK

#define UCLK 48000000


// Memory control 

#define BWSCON    0x48000000  //Bus width & wait status

#define BANKCON0  0x48000004  //Boot ROM control

#define BANKCON1  0x48000008  //BANK1 control

#define BANKCON2  0x4800000c  //BANK2 cControl

#define BANKCON3  0x48000010  //BANK3 control

#define BANKCON4  0x48000014  //BANK4 control

#define BANKCON5  0x48000018  //BANK5 control

#define BANKCON6  0x4800001c  //BANK6 control

#define BANKCON7  0x48000020  //BANK7 control

#define REFRESH   0x48000024  //DRAM/SDRAM refresh

#define BANKSIZE  0x48000028  //Flexible Bank Size

#define MRSRB6    0x4800002c  //Mode register set for SDRAM

#define MRSRB7    0x48000030  //Mode register set for SDRAM





// USB Host





// INTERRUPT

#define SRCPND     0x4a000000  //Interrupt request status

#define INTMOD     0x4a000004  //Interrupt mode control

#define INTMSK     0x4a000008  //Interrupt mask control

#define PRIORITY   0x4a00000a  //IRQ priority control

#define INTPND     0x4a000010  //Interrupt request status

// PENDING BIT

#define BIT_EINT0      (0x1)

#define BIT_EINT1      (0x1<<1)

#define BIT_EINT2      (0x1<<2)

#define BIT_EINT3      (0x1<<3)

#define BIT_EINT4_7    (0x1<<4)

#define BIT_EINT8_23   (0x1<<5)

#define BIT_NOTUSED6   (0x1<<6)

#define BIT_BAT_FLT    (0x1<<7)

#define BIT_TICK       (0x1<<8)

#define BIT_WDT        (0x1<<9)

#define BIT_TIMER0     (0x1<<10)

#define BIT_TIMER1     (0x1<<11)

#define BIT_TIMER2     (0x1<<12)

#define BIT_TIMER3     (0x1<<13)

#define BIT_TIMER4     (0x1<<14)

#define BIT_UART2      (0x1<<15)

#define BIT_LCD        (0x1<<16)

#define BIT_DMA0       (0x1<<17)

#define BIT_DMA1       (0x1<<18)

#define BIT_DMA2       (0x1<<19)

#define BIT_DMA3       (0x1<<20)

#define BIT_SDI        (0x1<<21)

#define BIT_SPI0       (0x1<<22)

#define BIT_UART1      (0x1<<23)

#define BIT_NOTUSED24  (0x1<<24)

#define BIT_USBD       (0x1<<25)

#define BIT_USBH       (0x1<<26)

#define BIT_IIC        (0x1<<27)

#define BIT_UART0      (0x1<<28)

#define BIT_SPI1       (0x1<<29)

#define BIT_RTCC       (0x1<<30)

#define BIT_ADC        (0x1<<31)

#define BIT_ALLMSK     (0xffffffff)


#define INTOFFSET  0x4a000014  //Interruot request source offset

#define SUBSRCPND  0x4a000018  //Sub source pending

#define INTSUBMSK  0x4a00001c  //Interrupt sub mask

#define BIT_SUB_ALLMSK (0x7ff)

#define BIT_SUB_ADC    (0x1<<10)

#define BIT_SUB_TC     (0x1<<9)

#define BIT_SUB_ERR2   (0x1<<8)

#define BIT_SUB_TXD2   (0x1<<7)

#define BIT_SUB_RXD2   (0x1<<6)

#define BIT_SUB_ERR1   (0x1<<5)

#define BIT_SUB_TXD1   (0x1<<4)

#define BIT_SUB_RXD1   (0x1<<3)

#define BIT_SUB_ERR0   (0x1<<2)

#define BIT_SUB_TXD0   (0x1<<1)

#define BIT_SUB_RXD0   (0x1<<0)





// DMA

#define DISRC0     0x4b000000  //DMA 0 Initial source

#define DISRCC0    0x4b000004  //DMA 0 Initial source control

#define DIDST0     0x4b000008  //DMA 0 Initial Destination

#define DIDSTC0    0x4b00000c  //DMA 0 Initial Destination control

#define DCON0      0x4b000010  //DMA 0 Control

#define DSTAT0     0x4b000014  //DMA 0 Status

#define DCSRC0     0x4b000018  //DMA 0 Current source

#define DCDST0     0x4b00001c  //DMA 0 Current destination

#define DMASKTRIG0 0x4b000020  //DMA 0 Mask trigger



#define DISRC1     0x4b000040  //DMA 1 Initial source

#define DISRCC1    0x4b000044  //DMA 1 Initial source control

#define DIDST1     0x4b000048  //DMA 1 Initial Destination

#define DIDSTC1    0x4b00004c  //DMA 1 Initial Destination control

#define DCON1      0x4b000050  //DMA 1 Control

#define DSTAT1     0x4b000054  //DMA 1 Status

#define DCSRC1     0x4b000058  //DMA 1 Current source

#define DCDST1     0x4b00005c  //DMA 1 Current destination

#define DMASKTRIG1 0x4b000060  //DMA 1 Mask trigger



#define DISRC2     0x4b000080  //DMA 2 Initial source

#define DISRCC2    0x4b000084  //DMA 2 Initial source control

#define DIDST2     0x4b000088  //DMA 2 Initial Destination

#define DIDSTC2    0x4b00008c  //DMA 2 Initial Destination control

#define DCON2      0x4b000090  //DMA 2 Control

#define DSTAT2     0x4b000094  //DMA 2 Status

#define DCSRC2     0x4b000098  //DMA 2 Current source

#define DCDST2     0x4b00009c  //DMA 2 Current destination

#define DMASKTRIG2 0x4b0000a0  //DMA 2 Mask trigger



#define DISRC3     0x4b0000c0  //DMA 3 Initial source

#define DISRCC3    0x4b0000c4  //DMA 3 Initial source control

#define DIDST3     0x4b0000c8  //DMA 3 Initial Destination

#define DIDSTC3    0x4b0000cc  //DMA 3 Initial Destination control

#define DCON3      0x4b0000d0  //DMA 3 Control

#define DSTAT3     0x4b0000d4  //DMA 3 Status

#define DCSRC3     0x4b0000d8  //DMA 3 Current source

#define DCDST3     0x4b0000dc  //DMA 3 Current destination

#define DMASKTRIG3 0x4b0000e0  //DMA 3 Mask trigger





// CLOCK & POWER MANAGEMENT

#define LOCKTIME   0x4c000000  //PLL lock time counter

#define MPLLCON    0x4c000004  //MPLL Control

#define UPLLCON    0x4c000008  //UPLL Control

#define CLKCON     0x4c00000c  //Clock generator control

#define CLKSLOW    0x4c000010  //Slow clock control

#define CLKDIVN    0x4c000014  //Clock divider control





// LCD CONTROLLER

#define LCDCON1    0x4d000000  //LCD control 1

#define LCDCON2    0x4d000004  //LCD control 2

#define LCDCON3    0x4d000008  //LCD control 3

#define LCDCON4    0x4d00000c  //LCD control 4

#define LCDCON5    0x4d000010  //LCD control 5

#define LCDSADDR1  0x4d000014  //STN/TFT Frame buffer start address 1

#define LCDSADDR2  0x4d000018  //STN/TFT Frame buffer start address 2

#define LCDSADDR3  0x4d00001c  //STN/TFT Virtual screen address set

#define REDLUT     0x4d000020  //STN Red lookup table

#define GREENLUT   0x4d000024  //STN Green lookup table 

#define BLUELUT    0x4d000028  //STN Blue lookup table

#define DITHMODE   0x4d00004c  //STN Dithering mode

#define TPAL       0x4d000050  //TFT Temporary palette

#define LCDINTPND  0x4d000054  //LCD Interrupt pending

#define LCDSRCPND  0x4d000058  //LCD Interrupt source

#define LCDINTMSK  0x4d00005c  //LCD Interrupt mask

#define LPCSEL     0x4d000060  //LPC3600 Control

#define PALETTE    0x4d000400  //Palette start address





// NAND flash

#define NFCONF     0x4e000000  //NAND Flash configuration

#define NFCMD      0x4e000004  //NADD Flash command

#define NFADDR     0x4e000008  //NAND Flash address

#define NFDATA     0x4e00000c  //NAND Flash data

#define NFSTAT     0x4e000010  //NAND Flash operation status

#define NFECC      0x4e000014  //NAND Flash ECC

#define NFECC0     0x4e000014

#define NFECC1     0x4e000015

#define NFECC2     0x4e000016




// UART

#define ULCON0     0x50000000  //UART 0 Line control

#define UCON0      0x50000004  //UART 0 Control

#define UFCON0     0x50000008  //UART 0 FIFO control

#define UMCON0     0x5000000c  //UART 0 Modem control

#define UTRSTAT0   0x50000010  //UART 0 Tx/Rx status

#define UERSTAT0   0x50000014  //UART 0 Rx error status

#define UFSTAT0    0x50000018  //UART 0 FIFO status

#define UMSTAT0    0x5000001c  //UART 0 Modem status

#define UBRDIV0    0x50000028  //UART 0 Baud rate divisor



#define ULCON1     0x50004000  //UART 1 Line control

#define UCON1      0x50004004  //UART 1 Control

#define UFCON1     0x50004008  //UART 1 FIFO control

#define UMCON1     0x5000400c  //UART 1 Modem control

#define UTRSTAT1   0x50004010  //UART 1 Tx/Rx status

#define UERSTAT1   0x50004014  //UART 1 Rx error status

#define UFSTAT1    0x50004018  //UART 1 FIFO status

#define UMSTAT1    0x5000401c  //UART 1 Modem status

#define UBRDIV1    0x50004028  //UART 1 Baud rate divisor



#define ULCON2     0x50008000  //UART 2 Line control

#define UCON2      0x50008004  //UART 2 Control

#define UFCON2     0x50008008  //UART 2 FIFO control

#define UMCON2     0x5000800c  //UART 2 Modem control

#define UTRSTAT2   0x50008010  //UART 2 Tx/Rx status