library IEEE;
use IEEE.std_logic_1164.all;

entity SUB is
    port (
        Q0: in STD_LOGIC;
        Q1: in STD_LOGIC;
        Q2: in STD_LOGIC;
        Q3: in STD_LOGIC;
        P0: in STD_LOGIC;
        P1: in STD_LOGIC;
        P2: in STD_LOGIC;
        P3: in STD_LOGIC;
        Y0: out STD_LOGIC;
        Y1: out STD_LOGIC;
        Y2: out STD_LOGIC;
        Y3: out STD_LOGIC
    );
end SUB;

architecture SUB_arch of SUB is
SIGNAL COUT1 , COUT2 , COUT3 :STD_LOGIC;
begin
Y0<=Q0 XOR P0;
COUT1<=(NOT Q0) AND P0;
Y1<=Q1 XOR P1 XOR COUT1;
COUT2<=((NOT Q1)AND P1) OR ((NOT Q1) AND COUT1) OR (P1 AND COUT1);
Y2<=Q2 XOR P2 XOR COUT2;
COUT3<=((NOT Q2)AND P2) OR ((NOT Q2) AND COUT2) OR (P2 AND COUT2);
Y3<=Q3 XOR P3 XOR COUT3;
end SUB_arch;