?? sfr62p.h
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#define ilvl0_ta0ic ta0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta0ic ta0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta0ic ta0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta0ic ta0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A1 receive interrupt control register
------------------------------------------------------*/
union byte_def ta1ic_addr;
#define ta1ic ta1ic_addr.byte
#define ilvl0_ta1ic ta1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta1ic ta1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta1ic ta1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta1ic ta1ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A2 receive interrupt control register
------------------------------------------------------*/
union byte_def ta2ic_addr;
#define ta2ic ta2ic_addr.byte
#define ilvl0_ta2ic ta2ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta2ic ta2ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta2ic ta2ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta2ic ta2ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A3 receive interrupt control register
------------------------------------------------------*/
union byte_def ta3ic_addr;
#define ta3ic ta3ic_addr.byte
#define ilvl0_ta3ic ta3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta3ic ta3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta3ic ta3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta3ic ta3ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A4 receive interrupt control register
------------------------------------------------------*/
union byte_def ta4ic_addr;
#define ta4ic ta4ic_addr.byte
#define ilvl0_ta4ic ta4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta4ic ta4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta4ic ta4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta4ic ta4ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B0 receive interrupt control register
------------------------------------------------------*/
union byte_def tb0ic_addr;
#define tb0ic tb0ic_addr.byte
#define ilvl0_tb0ic tb0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb0ic tb0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb0ic tb0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb0ic tb0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B1 receive interrupt control register
------------------------------------------------------*/
union byte_def tb1ic_addr;
#define tb1ic tb1ic_addr.byte
#define ilvl0_tb1ic tb1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb1ic tb1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb1ic tb1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb1ic tb1ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B2 receive interrupt control register
------------------------------------------------------*/
union byte_def tb2ic_addr;
#define tb2ic tb2ic_addr.byte
#define ilvl0_tb2ic tb2ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb2ic tb2ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb2ic tb2ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb2ic tb2ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
INT0 receive interrupt control register
------------------------------------------------------*/
union byte_def int0ic_addr;
#define int0ic int0ic_addr.byte
#define ilvl0_int0ic int0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int0ic int0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int0ic int0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int0ic int0ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int0ic int0ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT1 receive interrupt control register
------------------------------------------------------*/
union byte_def int1ic_addr;
#define int1ic int1ic_addr.byte
#define ilvl0_int1ic int1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int1ic int1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int1ic int1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int1ic int1ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int1ic int1ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT2 receive interrupt control register
------------------------------------------------------*/
union byte_def int2ic_addr;
#define int2ic int2ic_addr.byte
#define ilvl0_int2ic int2ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int2ic int2ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int2ic int2ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int2ic int2ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int2ic int2ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
Flash memory control register 1
------------------------------------------------------*/
union byte_def fmr1_addr;
#define fmr1 fmr1_addr.byte
#define fmr11 fmr1_addr.bit.b1 /* EW1 mode select bit */
#define fmr16 fmr1_addr.bit.b6 /* Lock bit status flag */
/*------------------------------------------------------
Flash memory control register 0
------------------------------------------------------*/
union byte_def fmr0_addr;
#define fmr0 fmr0_addr.byte
#define fmr00 fmr0_addr.bit.b0 /* RY/BY~ status flag */
#define fmr01 fmr0_addr.bit.b1 /* EW0 mode select bit */
#define fmr02 fmr0_addr.bit.b2 /* Lock bit disable bit */
#define fmr03 fmr0_addr.bit.b3 /* Flash memory reset bit */
#define fmr05 fmr0_addr.bit.b5 /* User ROM area select bit */
#define fmr06 fmr0_addr.bit.b6 /* Program status flag */
#define fmr07 fmr0_addr.bit.b7 /* Erase status flag */
/*------------------------------------------------------
Address match interrupt enable register 2
------------------------------------------------------*/
union byte_def aier2_addr;
#define aier2 aier2_addr.byte
#define aier20 aier2_addr.bit.b0 /* Address match interrupt 2 enable bit */
#define aier21 aier2_addr.bit.b1 /* Address match interrupt 3 enable bit */
/*------------------------------------------------------
Peripheral clock select register
------------------------------------------------------*/
union byte_def pclkr_addr;
#define pclkr pclkr_addr.byte
#define pclk0 pclkr_addr.bit.b0 /* TimerA,B clock select bit */
#define pclk1 pclkr_addr.bit.b1 /* SI/O clock select bit */
/*------------------------------------------------------
Timer B3,4,5 Count start flag
------------------------------------------------------*/
union byte_def tbsr_addr;
#define tbsr tbsr_addr.byte
#define tb3s tbsr_addr.bit.b5 /* Timer B3 count start flag */
#define tb4s tbsr_addr.bit.b6 /* Timer B4 count start flag */
#define tb5s tbsr_addr.bit.b7 /* Timer B5 count start flag */
/*------------------------------------------------------
Three-phase PWM control regester 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define invc0 invc0_addr.byte
#define inv00 invc0_addr.bit.b0 /* Effective interrupt output polarity select bit */
#define inv01 invc0_addr.bit.b1 /* Effective interrupt output specification bit */
#define inv02 invc0_addr.bit.b2 /* Mode select bit */
#define inv03 invc0_addr.bit.b3 /* Output control bit */
#define inv04 invc0_addr.bit.b4 /* Positive and negative phases concurrent L output disable function enable bit */
#define inv05 invc0_addr.bit.b5 /* Positive and negative phases concurrent L output detect flag */
#define inv06 invc0_addr.bit.b6 /* Modulation mode select bit */
#define inv07 invc0_addr.bit.b7 /* Software trigger bit */
/*------------------------------------------------------
Three-phase PWM control regester 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define invc1 invc1_addr.byte
#define inv10 invc1_addr.bit.b0 /* Timer Ai start trigger signal select bit */
#define inv11 invc1_addr.bit.b1 /* Timer A1-1,A2-1,A4-1 control bit */
#define inv12 invc1_addr.bit.b2 /* Dead time timer count source select bit */
#define inv13 invc1_addr.bit.b3 /* Carrier wave detect flag */
#define inv14 invc1_addr.bit.b4 /* Output porality control bit */
#define inv15 invc1_addr.bit.b5 /* Dead time invalid bit */
#define inv16 invc1_addr.bit.b6 /* Dead time timer trigger select bit */
#define inv17 invc1_addr.bit.b7 /* Waveform reflect timing select bit */
/*------------------------------------------------------
Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* U phase output buffer 0 */
#define dub0 idb0_addr.bit.b1 /* U~ phase output buffer 0 */
#define dv0 idb0_addr.bit.b2 /* V phase output buffer 0 */
#define dvb0 idb0_addr.bit.b3 /* V~ phase output buffer 0 */
#define dw0 idb0_addr.bit.b4 /* W phase output buffer 0 */
#define dwb0 idb0_addr.bit.b5 /* W~ phase output buffer 0 */
/*------------------------------------------------------
Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define idb1 idb1_addr.byte
#define du1 idb1_addr.bit.b0 /* U phase output buffer 1 */
#define dub1 idb1_addr.bit.b1 /* U~ phase output buffer 1 */
#define dv1 idb1_addr.bit.b2 /* V phase output buffer 1 */
#define dvb1 idb1_addr.bit.b3 /* V~ phase output buffer 1 */
#define dw1 idb1_addr.bit.b4 /* W phase output buffer 1 */
#define dwb1 idb1_addr.bit.b5 /* W~ phase output buffer 1 */
/*------------------------------------------------------
Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define dtt dtt_addr.byte
/*------------------------------------------------------------------
Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction when writing to this register.
-------------------------------------------------------------------*/
union byte_def ictb2_addr;
#define ictb2 ictb2_addr.byte
/*------------------------------------------------------
Timer B3 mode register
------------------------------------------------------*/
union byte_def tb3mr_addr;
#define tb3mr tb3mr_addr.byte
#define tmod0_tb3mr tb3mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb3mr tb3mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb3mr tb3mr_addr.bit.b2
#define mr1_tb3mr tb3mr_addr.bit.b3
#define mr2_tb3mr tb3mr_addr.bit.b4
#define mr3_tb3mr tb3mr_addr.bit.b5
#define tck0_tb3mr tb3mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb3mr tb3mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Timer B4 mode register
------------------------------------------------------*/
union byte_def tb4mr_addr;
#define tb4mr tb4mr_addr.byte
#define tmod0_tb4mr tb4mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb4mr tb4mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb4mr tb4mr_addr.bit.b2
#define mr1_tb4mr tb4mr_addr.bit.b3
#define mr3_tb4mr tb4mr_addr.bit.b5
#define tck0_tb4mr tb4mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb4mr tb4mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Timer B5 mode register
------------------------------------------------------*/
union byte_def tb5mr_addr;
#define tb5mr tb5mr_addr.byte
#define tmod0_tb5mr tb5mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb5mr tb5mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb5mr tb5mr_addr.bit.b2
#define mr1_tb5mr tb5mr_addr.bit.b3
#define mr3_tb5mr tb5mr_addr.bit.b5
#define tck0_tb5mr tb5mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb5mr tb5mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Interrupt request cause select register 2
------------------------------------------------------*/
union byte_def ifsr2a_addr;
#define ifsr2a ifsr2a_addr.byte
#define ifsr26 ifsr2a_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr27 ifsr2a_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
Interrupt request cause select register
------------------------------------------------------*/
union byte_def ifsr_addr;
#define ifsr ifsr_addr.byte
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