/* * These files are taken from the MCF523X source code example package * which is available on the Freescale website. Freescale explicitly  * grants the redistribution and modification of these source files. * The complete licensing information is available in the file  * LICENSE_FREESCALE.TXT. * * File:	mcf523x_gpio.h * Purpose:	Register and bit definitions for the MCF523X * * Notes:	 *	 */#ifndef __MCF523X_GPIO_H__#define __MCF523X_GPIO_H__/*********************************************************************** General Purpose I/O (GPIO)**********************************************************************//* Register read/write macros */#define MCF_GPIO_PODR_ADDR        (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))#define MCF_GPIO_PODR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))#define MCF_GPIO_PODR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))#define MCF_GPIO_PODR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))#define MCF_GPIO_PODR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))#define MCF_GPIO_PODR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))#define MCF_GPIO_PODR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))#define MCF_GPIO_PODR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))#define MCF_GPIO_PODR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))#define MCF_GPIO_PODR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))#define MCF_GPIO_PODR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))#define MCF_GPIO_PODR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))#define MCF_GPIO_PODR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))#define MCF_GPIO_PDDR_APDDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))#define MCF_GPIO_PDDR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))#define MCF_GPIO_PDDR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))#define MCF_GPIO_PDDR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))#define MCF_GPIO_PDDR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))#define MCF_GPIO_PDDR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))#define MCF_GPIO_PDDR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))#define MCF_GPIO_PDDR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))#define MCF_GPIO_PDDR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))#define MCF_GPIO_PDDR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))#define MCF_GPIO_PDDR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))#define MCF_GPIO_PDDR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))#define MCF_GPIO_PDDR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))#define MCF_GPIO_PPDSDR_ADDR      (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))#define MCF_GPIO_PPDSDR_DATAH     (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))#define MCF_GPIO_PPDSDR_DATAL     (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))#define MCF_GPIO_PPDSDR_BUSCTL    (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))#define MCF_GPIO_PPDSDR_BS        (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))#define MCF_GPIO_PPDSDR_FECI2C    (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))#define MCF_GPIO_PPDSDR_CS        (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))#define MCF_GPIO_PPDSDR_SDRAM     (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))#define MCF_GPIO_PPDSDR_UARTH     (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))#define MCF_GPIO_PPDSDR_UARTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))#define MCF_GPIO_PPDSDR_QSPI      (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))#define MCF_GPIO_PPDSDR_TIMER     (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))#define MCF_GPIO_PPDSDR_ETPU      (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))#define MCF_GPIO_PCLRR_ADDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))#define MCF_GPIO_PCLRR_DATAH      (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))#define MCF_GPIO_PCLRR_DATAL      (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))#define MCF_GPIO_PCLRR_BUSCTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))#define MCF_GPIO_PCLRR_BS         (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))#define MCF_GPIO_PCLRR_CS         (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))#define MCF_GPIO_PCLRR_SDRAM      (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))#define MCF_GPIO_PCLRR_FECI2C     (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))#define MCF_GPIO_PCLRR_UARTH      (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))#define MCF_GPIO_PCLRR_UARTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))#define MCF_GPIO_PCLRR_QSPI       (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))#define MCF_GPIO_PCLRR_TIMER      (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))#define MCF_GPIO_PCLRR_ETPU       (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))#define MCF_GPIO_PAR_AD           (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))#define MCF_GPIO_PAR_BUSCTL       (*(vuint16*)(void*)(&__IPSBAR[0x100042]))#define MCF_GPIO_PAR_BS           (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))#define MCF_GPIO_PAR_CS           (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))#define MCF_GPIO_PAR_SDRAM        (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))#define MCF_GPIO_PAR_FECI2C       (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))#define MCF_GPIO_PAR_UART         (*(vuint16*)(void*)(&__IPSBAR[0x100048]))#define MCF_GPIO_PAR_QSPI         (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))#define MCF_GPIO_PAR_TIMER        (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))#define MCF_GPIO_PAR_ETPU         (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))#define MCF_GPIO_DSCR_EIM         (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))#define MCF_GPIO_DSCR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))#define MCF_GPIO_DSCR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))#define MCF_GPIO_DSCR_UART        (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))#define MCF_GPIO_DSCR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))#define MCF_GPIO_DSCR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */#define MCF_GPIO_PODR_ADDR_PODR_ADDR5            (0x20)#define MCF_GPIO_PODR_ADDR_PODR_ADDR6            (0x40)#define MCF_GPIO_PODR_ADDR_PODR_ADDR7            (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */#define MCF_GPIO_PODR_DATAH_PODR_DATAH0          (0x01)#define MCF_GPIO_PODR_DATAH_PODR_DATAH1          (0x02)#define MCF_GPIO_PODR_DATAH_PODR_DATAH2          (0x04)#define MCF_GPIO_PODR_DATAH_PODR_DATAH3          (0x08)#define MCF_GPIO_PODR_DATAH_PODR_DATAH4          (0x10)#define MCF_GPIO_PODR_DATAH_PODR_DATAH5          (0x20)#define MCF_GPIO_PODR_DATAH_PODR_DATAH6          (0x40)#define MCF_GPIO_PODR_DATAH_PODR_DATAH7          (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */#define MCF_GPIO_PODR_DATAL_PODR_DATAL0          (0x01)#define MCF_GPIO_PODR_DATAL_PODR_DATAL1          (0x02)#define MCF_GPIO_PODR_DATAL_PODR_DATAL2          (0x04)#define MCF_GPIO_PODR_DATAL_PODR_DATAL3          (0x08)#define MCF_GPIO_PODR_DATAL_PODR_DATAL4          (0x10)#define MCF_GPIO_PODR_DATAL_PODR_DATAL5          (0x20)#define MCF_GPIO_PODR_DATAL_PODR_DATAL6          (0x40)#define MCF_GPIO_PODR_DATAL_PODR_DATAL7          (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0        (0x01)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1        (0x02)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2        (0x04)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3        (0x08)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4        (0x10)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5        (0x20)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6        (0x40)#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7        (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_BS */#define MCF_GPIO_PODR_BS_PODR_BS0                (0x01)#define MCF_GPIO_PODR_BS_PODR_BS1                (0x02)#define MCF_GPIO_PODR_BS_PODR_BS2                (0x04)#define MCF_GPIO_PODR_BS_PODR_BS3                (0x08)/* Bit definitions and macros for MCF_GPIO_PODR_CS */#define MCF_GPIO_PODR_CS_PODR_CS1                (0x02)#define MCF_GPIO_PODR_CS_PODR_CS2                (0x04)#define MCF_GPIO_PODR_CS_PODR_CS3                (0x08)#define MCF_GPIO_PODR_CS_PODR_CS4                (0x10)#define MCF_GPIO_PODR_CS_PODR_CS5                (0x20)#define MCF_GPIO_PODR_CS_PODR_CS6                (0x40)#define MCF_GPIO_PODR_CS_PODR_CS7                (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0          (0x01)#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1          (0x02)#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2          (0x04)#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3          (0x08)#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4          (0x10)#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5          (0x20)/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0        (0x01)#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1        (0x02)#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2        (0x04)#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3        (0x08)/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */#define MCF_GPIO_PODR_UARTH_PODR_UARTH0          (0x01)#define MCF_GPIO_PODR_UARTH_PODR_UARTH1          (0x02)/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */#define MCF_GPIO_PODR_UARTL_PODR_UARTL0          (0x01)#define MCF_GPIO_PODR_UARTL_PODR_UARTL1          (0x02)#define MCF_GPIO_PODR_UARTL_PODR_UARTL2          (0x04)#define MCF_GPIO_PODR_UARTL_PODR_UARTL3          (0x08)#define MCF_GPIO_PODR_UARTL_PODR_UARTL4          (0x10)#define MCF_GPIO_PODR_UARTL_PODR_UARTL5          (0x20)#define MCF_GPIO_PODR_UARTL_PODR_UARTL6          (0x40)#define MCF_GPIO_PODR_UARTL_PODR_UARTL7          (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */#define MCF_GPIO_PODR_QSPI_PODR_QSPI0            (0x01)#define MCF_GPIO_PODR_QSPI_PODR_QSPI1            (0x02)#define MCF_GPIO_PODR_QSPI_PODR_QSPI2            (0x04)#define MCF_GPIO_PODR_QSPI_PODR_QSPI3            (0x08)#define MCF_GPIO_PODR_QSPI_PODR_QSPI4            (0x10)/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */#define MCF_GPIO_PODR_TIMER_PODR_TIMER0          (0x01)#define MCF_GPIO_PODR_TIMER_PODR_TIMER1          (0x02)#define MCF_GPIO_PODR_TIMER_PODR_TIMER2          (0x04)#define MCF_GPIO_PODR_TIMER_PODR_TIMER3          (0x08)#define MCF_GPIO_PODR_TIMER_PODR_TIMER4          (0x10)#define MCF_GPIO_PODR_TIMER_PODR_TIMER5          (0x20)#define MCF_GPIO_PODR_TIMER_PODR_TIMER6          (0x40)#define MCF_GPIO_PODR_TIMER_PODR_TIMER7          (0x80)/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */#define MCF_GPIO_PODR_ETPU_PODR_ETPU0            (0x01)#define MCF_GPIO_PODR_ETPU_PODR_ETPU1            (0x02)#define MCF_GPIO_PODR_ETPU_PODR_ETPU2            (0x04)/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5          (0x20)#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6          (0x40)#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7          (0x80)/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0          (0x01)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1          (0x02)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2          (0x04)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3          (0x08)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4          (0x10)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5          (0x20)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6          (0x40)#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7          (0x80)/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0          (0x01)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1          (0x02)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2          (0x04)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3          (0x08)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4          (0x10)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5          (0x20)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6          (0x40)#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7          (0x80)/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0        (0x01)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1        (0x02)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2        (0x04)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3        (0x08)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4        (0x10)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5        (0x20)#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6        (0x40)