/*    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.    This file is part of the FreeRTOS distribution.    FreeRTOS is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    FreeRTOS is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with FreeRTOS; if not, write to the Free Software    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA    A special exception to the GPL can be applied should you wish to distribute    a combined work that includes FreeRTOS, without being obliged to provide    the source code for any proprietary components.  See the licensing section    of http://www.FreeRTOS.org for full details of how and when the exception    can be applied.    ***************************************************************************    See http://www.FreeRTOS.org for documentation, latest information, license    and contact details.  Please ensure to read the configuration and relevant    port sections of the online documentation.    ****************************************************************************/#include "mcf5xxx.h"#include "mcf523x.h"/* Function prototypes */void            init_main( void );static void     disable_interrupts( void );static void     disable_watchdog_timer( void );static void     disable_cache( void );static void     init_ipsbar( void );static void     init_basics( void );static void     init_clock_config( void );static void     init_chip_selects( void );static void     init_bus_config( void );static void     init_cache( void );static void     init_eport( void );static void     init_flexcan( void );static void     init_power_management( void );static void     init_dma_timers( void );static void     init_interrupt_timers( void );static void     init_watchdog_timers( void );static void     init_pin_assignments( void );static void     init_sdram_controller( void );static void     init_interrupt_controller( void );/********************************************************************** init_main - Main entry point for initialisation code               ***********************************************************************/voidinit_main( void ){    /* Initialise base address of peripherals, VBR, etc */    init_ipsbar(  );    init_basics(  );    init_clock_config(  );    /* Disable interrupts, watchdog timer, cache */    disable_interrupts(  );    disable_watchdog_timer(  );    disable_cache(  );    /* Initialise individual modules */    init_chip_selects(  );    init_bus_config(  );    init_cache(  );    init_eport(  );    init_flexcan(  );    init_power_management(  );    init_dma_timers(  );    init_interrupt_timers(  );    init_watchdog_timers(  );    init_pin_assignments(  );    init_sdram_controller(  );    /* Initialise interrupt controller */    init_interrupt_controller(  );}/********************************************************************** disable_interrupts - Disable all interrupt sources                 ***********************************************************************/static voiddisable_interrupts( void ){    vuint8         *p;    int             i;    /* Set ICR008-ICR063 to 0x0 */    p = ( vuint8 * ) & MCF_INTC0_ICR8;    for( i = 8; i <= 63; i++ )        *p++ = 0x0;    /* Set ICR108-ICR163 to 0x0 */    p = ( vuint8 * ) & MCF_INTC1_ICR8;    for( i = 108; i <= 163; i++ )        *p++ = 0x0;}/********************************************************************** disable_watchdog_timer - Disable system watchdog timer             ***********************************************************************/static voiddisable_watchdog_timer( void ){    /* Disable Core Watchdog Timer */    MCF_SCM_CWCR = 0;}/********************************************************************** disable_cache - Disable and invalidate cache                       ***********************************************************************/static voiddisable_cache( void ){    asm ( "move.l   #0x01000000, %d0" );    asm ( "movec    %d0, %CACR" );}/********************************************************************** init_basics - Configuration Information & VBR                      ***********************************************************************/static voidinit_basics( void ){    int             i;    extern uint32   __RAMVEC[];    extern uint32   __ROMVEC[];    /* Transfer size not driven on SIZ[1:0] pins during external cycles       Processor Status (PST) and Debug Data (DDATA) functions disabled       Bus monitor disabled       Output pads configured for full strength     */    MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;    /* Set up RAM vectors */    for( i = 0; i < 256; i++ )    {        __RAMVEC[i] = __ROMVEC[i];    }    asm( "move.l   %0,%%d0": :"i"( __RAMVEC ) );    asm( "movec    %d0,%vbr" );}/********************************************************************** init_clock_config - Clock Module                                   ***********************************************************************/static voidinit_clock_config( void ){    /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)       MFD = 0, RFD = 1       Bus clock frequency = 25.00 MHz       Processor clock frequency = 2 x bus clock = 50.00 MHz       Frequency Modulation disabled       Loss of clock detection disabled       Reset/Interrupt on loss of lock disabled     */    MCF_FMPLL_SYNCR = 0x00100000;       /* Set RFD=RFD+1 to avoid frequency overshoot */    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */        ;    MCF_FMPLL_SYNCR = 0x00080000;       /* Set desired RFD */    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */        ;}/********************************************************************** init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     ***********************************************************************/static voidinit_ipsbar( void ){    extern int  __SRAM;    /* Base address of internal peripherals (IPSBAR) = 0x40000000       Note: Processor powers up with IPS base address = 0x40000000       Write to IPS base + 0x00000000 to set new value     */    *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;    /* Configure RAMBAR in SCM module and allow dual-ported access. */    MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;}/********************************************************************** init_chip_selects - Chip Select Module                             ***********************************************************************/static voidinit_chip_selects( void ){    extern void __FLASH;    uint32 FLASH_ADDR = (uint32)&__FLASH;    /* Chip Select 0 - External Flash */    MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );    MCF_CS_CSCR0 = ( 0                     | MCF_CS_CSCR_IWS( 6 )                     | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;    /* Chip Select 1 disabled (CSMR1[V] = 0) */    MCF_CS_CSAR1 = 0;    MCF_CS_CSMR1 = 0;    MCF_CS_CSCR1 = 0;    /* Chip Select 2 disabled (CSMR2[V] = 0) */    MCF_CS_CSAR2 = 0;    MCF_CS_CSMR2 = 0;    MCF_CS_CSCR2 = 0;    /* Chip Select 3 disabled (CSMR3[V] = 0) */    MCF_CS_CSAR3 = 0;    MCF_CS_CSMR3 = 0;    MCF_CS_CSCR3 = 0;    /* Chip Select 4 disabled (CSMR4[V] = 0) */    MCF_CS_CSAR4 = 0;    MCF_CS_CSMR4 = 0;    MCF_CS_CSCR4 = 0;    /* Chip Select 5 disabled (CSMR5[V] = 0) */    MCF_CS_CSAR5 = 0;    MCF_CS_CSMR5 = 0;    MCF_CS_CSCR5 = 0;    /* Chip Select 6 disabled (CSMR6[V] = 0) */    MCF_CS_CSAR6 = 0;    MCF_CS_CSMR6 = 0;    MCF_CS_CSCR6 = 0;    /* Chip Select 7 disabled (CSMR7[V] = 0) */    MCF_CS_CSAR7 = 0;    MCF_CS_CSMR7 = 0;    MCF_CS_CSCR7 = 0;}/********************************************************************** init_bus_config - Internal Bus Arbitration                         ***********************************************************************/static voidinit_bus_config( void ){    /* Use round robin arbitration scheme       Assigned priorities (highest first):       Ethernet       DMA Controller       ColdFire Core       DMA bandwidth control disabled       Park on last active bus master     */    MCF_SCM_MPARK =        MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |        MCF_SCM_MPARK_M1_PRTY( 0x1 );}/********************************************************************** init_cache - Instruction/Data Cache                                ***********************************************************************/static voidinit_cache( void ){    /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache       ACR0: Don't cache accesses to 16 MB memory region at address $20000000       ACR1: Don't cache accesses to 1 GB memory region at address $40000000       CACR: Cache accesses to the rest of memory    */    asm("move.l   #0x80000000,%d0");    asm("movec    %d0,%CACR");    asm("move.l   #0x2000c040,%d0");    asm("movec    %d0,%ACR0");    asm("move.l   #0x403fc040,%d0");    asm("movec    %d0,%ACR1");    /* Instruction/Data cache disabled. */    //asm( "move.l   #0x00000000, %d0" );    //asm( "movec    %d0,%cacr" );}/********************************************************************** init_eport - Edge Port Module (EPORT)                              ***********************************************************************/static voidinit_eport( void ){    /* Pins 1-7 configured as GPIO inputs */    MCF_EPORT_EPPAR = 0;    MCF_EPORT_EPDDR = 0;    MCF_EPORT_EPIER = 0;}/********************************************************************** init_flexcan - FlexCAN Module                                      ***********************************************************************/static voidinit_flexcan( void ){    /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */    MCF_CAN_IMASK0 = 0;    MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );    MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );    MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );    MCF_CAN_CANCTRL0 = 0;    MCF_CAN_CANMCR0 =        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );    /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */    MCF_CAN_IMASK1 = 0;    MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );    MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );    MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );    MCF_CAN_CANCTRL1 = 0;    MCF_CAN_CANMCR1 =        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );}/********************************************************************** init_power_management - Power Management                           ***********************************************************************/static voidinit_power_management( void ){    /* On executing STOP instruction, processor enters RUN mode       Mode is exited when an interrupt of level 1 or higher is received     */    MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;    MCF_CCM_LPCR = 0;}/********************************************************************** init_sdram_controller - SDRAM Controller                           ***********************************************************************/static voidinit_sdram_controller( void ){    extern void __SDRAM;    uint32 SDRAM_ADDR = (uint32)&__SDRAM;    int             i;    /*     * Check to see if the SDRAM has already been initialized     * by a run control tool     */    if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )    {        /* Initialize DRAM Control Register: DCR */