MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |                           MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );        /* Initialize DACR0 */        MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |                             MCF_SDRAMC_DACR0_CASL( 1 ) |                             MCF_SDRAMC_DACR0_CBM( 3 ) |                             MCF_SDRAMC_DACR0_PS( 0 ) );        /* Initialize DMR0 */        MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );        /* Set IP (bit 3) in DACR */        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;        /* Wait 30ns to allow banks to precharge */        for( i = 0; i < 5; i++ )        {            asm volatile    ( " nop" );        }        /* Write to this block to initiate precharge */        *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;        /* Set RE (bit 15) in DACR */        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;        /* Wait for at least 8 auto refresh cycles to occur */        for( i = 0; i < 2000; i++ )        {            asm volatile    ( "nop" );        }        /* Finish the configuration by issuing the IMRS. */        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;        /* Write to the SDRAM Mode Register */        *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;    }}/********************************************************************** init_dma_timers - DMA Timer Modules                                ***********************************************************************/static voidinit_dma_timers( void ){    /* DMA Timer 0 disabled (DTMR0[RST] = 0) */    MCF_TIMER_DTMR0 = 0;    MCF_TIMER_DTXMR0 = 0;    MCF_TIMER_DTRR0 = 0xffffffff;    /* DMA Timer 1 disabled (DTMR1[RST] = 0) */    MCF_TIMER_DTMR1 = 0;    MCF_TIMER_DTXMR1 = 0;    MCF_TIMER_DTRR1 = 0xffffffff;    /* DMA Timer 2 disabled (DTMR2[RST] = 0) */    MCF_TIMER_DTMR2 = 0;    MCF_TIMER_DTXMR2 = 0;    MCF_TIMER_DTRR2 = 0xffffffff;    /* DMA Timer 3 disabled (DTMR3[RST] = 0) */    MCF_TIMER_DTMR3 = 0;    MCF_TIMER_DTXMR3 = 0;    MCF_TIMER_DTRR3 = 0xffffffff;}/*********************************************************************** init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  ************************************************************************/static voidinit_interrupt_timers( void ){    /* PIT0 disabled (PCSR0[EN]=0) */    MCF_PIT_PCSR0 = 0;    /* PIT1 disabled (PCSR1[EN]=0) */    MCF_PIT_PCSR1 = 0;    /* PIT2 disabled (PCSR2[EN]=0) */    MCF_PIT_PCSR2 = 0;    /* PIT3 disabled (PCSR3[EN]=0) */    MCF_PIT_PCSR3 = 0;}/********************************************************************** init_watchdog_timers - Watchdog Timer Modules                      ***********************************************************************/static voidinit_watchdog_timers( void ){    /* Watchdog Timer disabled (WCR[EN]=0)       NOTE: WCR and WMR cannot be written again until after the       processor is reset.     */    MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;    MCF_WTM_WMR = 0xffff;    /* Core Watchdog Timer disabled (CWCR[CWE]=0) */    MCF_SCM_CWCR = 0;}/********************************************************************** init_interrupt_controller - Interrupt Controller                   ***********************************************************************/static voidinit_interrupt_controller( void ){    /* Configured interrupt sources in order of priority...       Level 7:  External interrupt /IRQ7, (initially masked)       Level 6:  External interrupt /IRQ6, (initially masked)       Level 5:  External interrupt /IRQ5, (initially masked)       Level 4:  External interrupt /IRQ4, (initially masked)       Level 3:  External interrupt /IRQ3, (initially masked)       Level 2:  External interrupt /IRQ2, (initially masked)       Level 1:  External interrupt /IRQ1, (initially masked)     */    MCF_INTC0_ICR1 = 0;    MCF_INTC0_ICR2 = 0;    MCF_INTC0_ICR3 = 0;    MCF_INTC0_ICR4 = 0;    MCF_INTC0_ICR5 = 0;    MCF_INTC0_ICR6 = 0;    MCF_INTC0_ICR7 = 0;    MCF_INTC0_ICR8 = 0;    MCF_INTC0_ICR9 = 0;    MCF_INTC0_ICR10 = 0;    MCF_INTC0_ICR11 = 0;    MCF_INTC0_ICR12 = 0;    MCF_INTC0_ICR13 = 0;    MCF_INTC0_ICR14 = 0;    MCF_INTC0_ICR15 = 0;    MCF_INTC0_ICR17 = 0;    MCF_INTC0_ICR18 = 0;    MCF_INTC0_ICR19 = 0;    MCF_INTC0_ICR20 = 0;    MCF_INTC0_ICR21 = 0;    MCF_INTC0_ICR22 = 0;    MCF_INTC0_ICR23 = 0;    MCF_INTC0_ICR24 = 0;    MCF_INTC0_ICR25 = 0;    MCF_INTC0_ICR26 = 0;    MCF_INTC0_ICR27 = 0;    MCF_INTC0_ICR28 = 0;    MCF_INTC0_ICR29 = 0;    MCF_INTC0_ICR30 = 0;    MCF_INTC0_ICR31 = 0;    MCF_INTC0_ICR32 = 0;    MCF_INTC0_ICR33 = 0;    MCF_INTC0_ICR34 = 0;    MCF_INTC0_ICR35 = 0;    MCF_INTC0_ICR36 = 0;    MCF_INTC0_ICR37 = 0;    MCF_INTC0_ICR38 = 0;    MCF_INTC0_ICR39 = 0;    MCF_INTC0_ICR40 = 0;    MCF_INTC0_ICR41 = 0;    MCF_INTC0_ICR42 = 0;    MCF_INTC0_ICR43 = 0;    MCF_INTC0_ICR44 = 0;    MCF_INTC0_ICR45 = 0;    MCF_INTC0_ICR46 = 0;    MCF_INTC0_ICR47 = 0;    MCF_INTC0_ICR48 = 0;    MCF_INTC0_ICR49 = 0;    MCF_INTC0_ICR50 = 0;    MCF_INTC0_ICR51 = 0;    MCF_INTC0_ICR52 = 0;    MCF_INTC0_ICR53 = 0;    MCF_INTC0_ICR54 = 0;    MCF_INTC0_ICR55 = 0;    MCF_INTC0_ICR56 = 0;    MCF_INTC0_ICR57 = 0;    MCF_INTC0_ICR58 = 0;    MCF_INTC0_ICR59 = 0;    MCF_INTC0_ICR60 = 0;    MCF_INTC1_ICR8 = 0;    MCF_INTC1_ICR9 = 0;    MCF_INTC1_ICR10 = 0;    MCF_INTC1_ICR11 = 0;    MCF_INTC1_ICR12 = 0;    MCF_INTC1_ICR13 = 0;    MCF_INTC1_ICR14 = 0;    MCF_INTC1_ICR15 = 0;    MCF_INTC1_ICR16 = 0;    MCF_INTC1_ICR17 = 0;    MCF_INTC1_ICR18 = 0;    MCF_INTC1_ICR19 = 0;    MCF_INTC1_ICR20 = 0;    MCF_INTC1_ICR21 = 0;    MCF_INTC1_ICR22 = 0;    MCF_INTC1_ICR23 = 0;    MCF_INTC1_ICR24 = 0;    MCF_INTC1_ICR25 = 0;    MCF_INTC1_ICR27 = 0;    MCF_INTC1_ICR28 = 0;    MCF_INTC1_ICR29 = 0;    MCF_INTC1_ICR30 = 0;    MCF_INTC1_ICR31 = 0;    MCF_INTC1_ICR32 = 0;    MCF_INTC1_ICR33 = 0;    MCF_INTC1_ICR34 = 0;    MCF_INTC1_ICR35 = 0;    MCF_INTC1_ICR36 = 0;    MCF_INTC1_ICR37 = 0;    MCF_INTC1_ICR38 = 0;    MCF_INTC1_ICR39 = 0;    MCF_INTC1_ICR40 = 0;    MCF_INTC1_ICR41 = 0;    MCF_INTC1_ICR42 = 0;    MCF_INTC1_ICR59 = 0;    MCF_INTC0_IMRH = 0xffffffff;    MCF_INTC0_IMRL =        MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |        MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |        MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |        MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |        MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |        MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |        MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |        MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |        MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |        MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |        MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |        MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |        MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |        MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |        MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |        MCF_INTC0_IMRL_INT_MASK1;    MCF_INTC1_IMRH = 0xffffffff;    MCF_INTC1_IMRL =        MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |        MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |        MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |        MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |        MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |        MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |        MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |        MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |        MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |        MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |        MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |        MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |        MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |        MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |        MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |        MCF_INTC1_IMRL_INT_MASK1;}/********************************************************************** init_pin_assignments - Pin Assignment and General Purpose I/O      ***********************************************************************/static voidinit_pin_assignments( void ){    /* Pin assignments for port ADDR       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_APDDR = 0;    MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23        | MCF_GPIO_PAR_AD_PAR_ADDR22        | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;    /* Pin assignments for ports DATAH and DATAL       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_DATAH = 0;    MCF_GPIO_PDDR_DATAL = 0;    /* Pin assignments for port BUSCTL       Pin /OE        : External bus output enable, /OE       Pin /TA        : External bus transfer acknowledge, /TA       Pin /TEA       : External bus transfer error acknowledge, /TEA       Pin R/W        : External bus read/write indication, R/W       Pin TSIZ1      : External bus transfer size TSIZ1 or DMA acknowledge /DACK1       Pin TSIZ0      : External bus transfer size TSIZ0 or DMA acknowledge /DACK0       Pin /TS        : External bus transfer start, /TS       Pin /TIP       : External bus transfer in progess, /TIP     */    MCF_GPIO_PDDR_BUSCTL = 0;    MCF_GPIO_PAR_BUSCTL =        MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |        MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |        MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |        MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |        MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );    /* Pin assignments for port BS       Pin /BS3       : External byte strobe /BS3       Pin /BS2       : External byte strobe /BS2       Pin /BS1       : External byte strobe /BS1       Pin /BS0       : External byte strobe /BS0     */    MCF_GPIO_PDDR_BS = 0;    MCF_GPIO_PAR_BS =        MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |        MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;    /* Pin assignments for port CS       Pin /CS7       : Chip select /CS7       Pin /CS6       : Chip select /CS6       Pin /CS5       : Chip select /CS5       Pin /CS4       : Chip select /CS4       Pin /CS3       : Chip select /CS3       Pin /CS2       : Chip select /CS2       Pin /CS1       : Chip select /CS1     */    MCF_GPIO_PDDR_CS = 0;    MCF_GPIO_PAR_CS =        MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |        MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |        MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |        MCF_GPIO_PAR_CS_PAR_CS1;    /* Pin assignments for port SDRAM       Pin /SD_WE     : SDRAM controller /SD_WE       Pin /SD_SCAS   : SDRAM controller /SD_SCAS       Pin /SD_SRAS   : SDRAM controller /SD_SRAS       Pin /SD_SCKE   : SDRAM controller /SD_SCKE       Pin /SD_CS1    : SDRAM controller /SD_CS1       Pin /SD_CS0    : SDRAM controller /SD_CS0     */    MCF_GPIO_PDDR_SDRAM = 0;    MCF_GPIO_PAR_SDRAM =        MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |        MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |        MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;    /* Pin assignments for port FECI2C       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_FECI2C = 0;    MCF_GPIO_PAR_FECI2C =        MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;    /* Pin assignments for port UARTL       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_UARTL = 0;    MCF_GPIO_PAR_UART = 0;    /* Pin assignments for port UARTH       Pin U2TXD      : GPIO input       Pin U2RXD      : GPIO input       Pin /IRQ2      : Interrupt request /IRQ2 or GPIO     */    MCF_GPIO_PDDR_UARTH = 0;    /* Pin assignments for port QSPI       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_QSPI = 0;    MCF_GPIO_PAR_QSPI = 0;    /* Pin assignments for port TIMER       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_TIMER = 0;    MCF_GPIO_PAR_TIMER = 0;    /* Pin assignments for port ETPU       Pins are all GPIO inputs     */    MCF_GPIO_PDDR_ETPU = 0;    MCF_GPIO_PAR_ETPU = 0;}