?? io_map.h
字號:
struct {
word grpFRZ :2;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
} MergedBits;
} ATDCTL23STR;
extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);
#define ATDCTL23 _ATDCTL23.Word
#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0
#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1
#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO
#define ATDCTL23_S1C _ATDCTL23.Bits.S1C
#define ATDCTL23_S2C _ATDCTL23.Bits.S2C
#define ATDCTL23_S4C _ATDCTL23.Bits.S4C
#define ATDCTL23_S8C _ATDCTL23.Bits.S8C
#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF
#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE
#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE
#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP
#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE
#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI
#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC
#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU
#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ
/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/
union {
byte Byte;
struct {
byte PRS0 :1; /* ATD Clock Prescaler 0 */
byte PRS1 :1; /* ATD Clock Prescaler 1 */
byte PRS2 :1; /* ATD Clock Prescaler 2 */
byte PRS3 :1; /* ATD Clock Prescaler 3 */
byte PRS4 :1; /* ATD Clock Prescaler 4 */
byte SMP0 :1; /* Sample Time Select 0 */
byte SMP1 :1; /* Sample Time Select 1 */
byte SRES8 :1; /* A/D Resolution Select */
} Bits;
struct {
byte grpPRS :5;
byte grpSMP :2;
byte grpSRES_8 :1;
} MergedBits;
} ATDCTL4STR;
#define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte
#define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0
#define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1
#define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2
#define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3
#define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4
#define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0
#define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1
#define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8
#define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS
#define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP
/*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/
union {
byte Byte;
struct {
byte CA :1; /* Analog Input Channel Select Code A */
byte CB :1; /* Analog Input Channel Select Code B */
byte CC :1; /* Analog Input Channel Select Code C */
byte :1;
byte MULT :1; /* Multi-Channel Sample Mode */
byte SCAN :1; /* Continuous Conversion Sequence Mode */
byte DSGN :1; /* Signed/Unsigned Result Data Mode */
byte DJM :1; /* Result Register Data Justification Mode */
} Bits;
} ATDCTL5STR;
#define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte
#define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA
#define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB
#define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC
#define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT
#define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN
#define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN
#define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM
} Overlap_STR;
struct {
word CA :1; /* Analog Input Channel Select Code A */
word CB :1; /* Analog Input Channel Select Code B */
word CC :1; /* Analog Input Channel Select Code C */
word :1;
word MULT :1; /* Multi-Channel Sample Mode */
word SCAN :1; /* Continuous Conversion Sequence Mode */
word DSGN :1; /* Signed/Unsigned Result Data Mode */
word DJM :1; /* Result Register Data Justification Mode */
word PRS0 :1; /* ATD Clock Prescaler 0 */
word PRS1 :1; /* ATD Clock Prescaler 1 */
word PRS2 :1; /* ATD Clock Prescaler 2 */
word PRS3 :1; /* ATD Clock Prescaler 3 */
word PRS4 :1; /* ATD Clock Prescaler 4 */
word SMP0 :1; /* Sample Time Select 0 */
word SMP1 :1; /* Sample Time Select 1 */
word SRES8 :1; /* A/D Resolution Select */
} Bits;
struct {
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word grpPRS :5;
word grpSMP :2;
word grpSRES_8 :1;
} MergedBits;
} ATDCTL45STR;
extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);
#define ATDCTL45 _ATDCTL45.Word
#define ATDCTL45_CA _ATDCTL45.Bits.CA
#define ATDCTL45_CB _ATDCTL45.Bits.CB
#define ATDCTL45_CC _ATDCTL45.Bits.CC
#define ATDCTL45_MULT _ATDCTL45.Bits.MULT
#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN
#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN
#define ATDCTL45_DJM _ATDCTL45.Bits.DJM
#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0
#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1
#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2
#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3
#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4
#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0
#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1
#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8
#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS
#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP
/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/
union {
byte Byte;
struct {
byte BIT8 :1; /* Bit 8 */
byte BIT9 :1; /* Bit 9 */
byte BIT10 :1; /* Bit 10 */
byte BIT11 :1; /* Bit 11 */
byte BIT12 :1; /* Bit 12 */
byte BIT13 :1; /* Bit 13 */
byte BIT14 :1; /* Bit 14 */
byte BIT15 :1; /* Bit 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} ATDDR0HSTR;
#define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte
#define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8
#define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9
#define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10
#define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11
#define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12
#define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13
#define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14
#define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15
#define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8
#define ATDDR0H_BIT ATDDR0H_BIT_8
/*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/
union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte BIT6 :1; /* Bit 6 */
byte BIT7 :1; /* Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte grpBIT_6 :2;
} MergedBits;
} ATDDR0LSTR;
#define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte
#define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6
#define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7
#define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6
#define ATDDR0L_BIT ATDDR0L_BIT_6
} Overlap_STR;
struct {
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word BIT6 :1; /* Bit 6 */
word BIT7 :1; /* Bit 7 */
word BIT8 :1; /* Bit 8 */
word BIT9 :1; /* Bit 9 */
word BIT10 :1; /* Bit 10 */
word BIT11 :1; /* Bit 11 */
word BIT12 :1; /* Bit 12 */
word BIT13 :1; /* Bit 13 */
word BIT14 :1; /* Bit 14 */
word BIT15 :1; /* Bit 15 */
} Bits;
struct {
word :1;
word :1;
word :1;
word :1;
word :1;
word :1;
word grpBIT_6 :10;
} MergedBits;
} ATDDR0STR;
extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);
#define ATDDR0 _ATDDR0.Word
#define ATDDR0_BIT6 _?? 快捷鍵說明
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