}        /* Figure out errors */	if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))		cmd->error = MMC_ERR_BADCRC;	trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);	if (!trans || cmd->error != MMC_ERR_NONE) {		IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);		tasklet_schedule(&host->finish_task);		return;	}	host->status = HOST_S_DATA;	if (host->flags & HOST_F_DMA) {		u32 channel = DMA_CHANNEL(host);		/* Start the DMA as soon as the buffer gets something in it */		if (host->flags & HOST_F_RECV) {			u32 mask = SD_STATUS_DB | SD_STATUS_NE;			while((status & mask) != mask) 				status = au_readl(HOST_STATUS(host));		}		au1xxx_dbdma_start(channel);	}}static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) {	unsigned int pbus = get_au1x00_speed();	unsigned int divisor;	u32 config;	/* From databook:	   divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1	*/	pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);	pbus /= 2;	divisor = ((pbus / rate) / 2) - 1;	config = au_readl(HOST_CONFIG(host));	config &= ~(SD_CONFIG_DIV);	config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;	au_writel(config, HOST_CONFIG(host));	au_sync();}static int au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) {	int datalen = data->blocks * (1 << data->blksz_bits);	if (dma != 0) 		host->flags |= HOST_F_DMA;	if (data->flags & MMC_DATA_READ)		host->flags |= HOST_F_RECV;	else		host->flags |= HOST_F_XMIT;	if (host->mrq->stop) 		host->flags |= HOST_F_STOP;			host->dma.dir = DMA_BIDIRECTIONAL;	host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,				   data->sg_len, host->dma.dir);	if (host->dma.len == 0)		return MMC_ERR_TIMEOUT;	au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));		if (host->flags & HOST_F_DMA) {		int i;		u32 channel = DMA_CHANNEL(host);		au1xxx_dbdma_stop(channel);		for(i = 0; i < host->dma.len; i++) {			u32 ret = 0, flags = DDMA_FLAGS_NOIE;			struct scatterlist *sg = &data->sg[i];			int sg_len = sg->length;						int len = (datalen > sg_len) ? sg_len : datalen;			if (i == host->dma.len - 1)				flags = DDMA_FLAGS_IE;    			if (host->flags & HOST_F_XMIT){      				ret = au1xxx_dbdma_put_source_flags(channel, 					(void *) (page_address(sg->page) + 						  sg->offset), 					len, flags);			}    			else {      				ret = au1xxx_dbdma_put_dest_flags(channel, 					(void *) (page_address(sg->page) + 						  sg->offset), 					len, flags);			}    			if (!ret) 				goto dataerr;			datalen -= len;		}	}	else {		host->pio.index = 0;		host->pio.offset = 0;		host->pio.len = datalen;				if (host->flags & HOST_F_XMIT)			IRQ_ON(host, SD_CONFIG_TH);		else 			IRQ_ON(host, SD_CONFIG_NE);			//IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);	}	return MMC_ERR_NONE; dataerr:	dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); 	return MMC_ERR_TIMEOUT;} /* static void au1xmmc_request   This actually starts a command or data transaction*/static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) {	struct au1xmmc_host *host = mmc_priv(mmc);	int ret = MMC_ERR_NONE;	WARN_ON(irqs_disabled());	WARN_ON(host->status != HOST_S_IDLE);	host->mrq = mrq;	host->status = HOST_S_CMD;	bcsr->disk_leds &= ~(1 << 8);	if (mrq->data) {		FLUSH_FIFO(host);		ret = au1xmmc_prepare_data(host, mrq->data);	}	if (ret == MMC_ERR_NONE)		ret = au1xmmc_send_command(host, 0, mrq->cmd);	if (ret != MMC_ERR_NONE) {		mrq->cmd->error = ret;		au1xmmc_finish_request(host);	}}static void au1xmmc_reset_controller(struct au1xmmc_host *host) {	/* Apply the clock */	au_writel(SD_ENABLE_CE, HOST_ENABLE(host));        au_sync_delay(1);	au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));	au_sync_delay(5);	au_writel(~0, HOST_STATUS(host));	au_sync();	au_writel(0, HOST_BLKSIZE(host));	au_writel(0x001fffff, HOST_TIMEOUT(host));	au_sync();	au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));        au_sync();	au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));	au_sync_delay(1);	au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));	au_sync();	/* Configure interrupts */	au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));	au_sync();}	static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) {	struct au1xmmc_host *host = mmc_priv(mmc);	DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",	      host->id, ios->power_mode, ios->clock, ios->vdd, 	      ios->bus_mode);	if (ios->power_mode == MMC_POWER_OFF) 		au1xmmc_set_power(host, 0);	else if (ios->power_mode == MMC_POWER_ON) {		au1xmmc_set_power(host, 1);	}	if (ios->clock && ios->clock != host->clock) {		au1xmmc_set_clock(host, ios->clock);		host->clock = ios->clock;	}}static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs) {	struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;	u32 status;	/* Avoid spurious interrupts */	if (!host->mrq) 		return;	if (host->flags & HOST_F_STOP) 		SEND_STOP(host);	tasklet_schedule(&host->data_task);}#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)#define STATUS_DATA_IN  (SD_STATUS_NE)#define STATUS_DATA_OUT (SD_STATUS_TH)static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs) {  	u32 status;	int i, ret = 0;	disable_irq(AU1100_SD_IRQ);	for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {    		struct au1xmmc_host * host = au1xmmc_hosts[i];		u32 handled = 1;		status = au_readl(HOST_STATUS(host));		if (host->mrq && (status & STATUS_TIMEOUT)) {			if (status & SD_STATUS_RAT)  				host->mrq->cmd->error = MMC_ERR_TIMEOUT;						else if (status & SD_STATUS_DT) 				host->mrq->data->error = MMC_ERR_TIMEOUT;					/* In PIO mode, interrupts might still be enabled */			IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);			//IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);			tasklet_schedule(&host->finish_task);		}#if 0		else if (status & SD_STATUS_DD) {			/* Sometimes we get a DD before a NE in PIO mode */			if (!(host->flags & HOST_F_DMA) && 					(status & SD_STATUS_NE))				au1xmmc_receive_pio(host);			else {				au1xmmc_data_complete(host, status);				//tasklet_schedule(&host->data_task);			}		}#endif		else if (status & (SD_STATUS_CR)) {			if (host->status == HOST_S_CMD)				au1xmmc_cmd_complete(host,status);		}		else if (!(host->flags & HOST_F_DMA)) { 			if ((host->flags & HOST_F_XMIT) && 			    (status & STATUS_DATA_OUT))				au1xmmc_send_pio(host);			else if ((host->flags & HOST_F_RECV) && 			    (status & STATUS_DATA_IN))				au1xmmc_receive_pio(host);		}		else if (status & 0x203FBC70) {			DEBUG("Unhandled status %8.8x\n", host->id, status);			handled = 0;		}				au_writel(status, HOST_STATUS(host));		au_sync();		ret |= handled;	}	enable_irq(AU1100_SD_IRQ);	return ret;}static void au1xmmc_poll_event(unsigned long arg) {	struct au1xmmc_host *host = (struct au1xmmc_host *) arg;	int card = au1xmmc_card_inserted(host);        int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;	if (card != controller) {		host->flags &= ~HOST_F_ACTIVE;		if (card) host->flags |= HOST_F_ACTIVE;		mmc_detect_change(host->mmc);	}	if (host->mrq != NULL) {		u32 status = au_readl(HOST_STATUS(host));		DEBUG("PENDING - %8.8x\n", host->id, status);	}	mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);}static dbdev_tab_t au1xmmc_mem_dbdev = {	DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0};static void au1xmmc_init_dma(struct au1xmmc_host *host) {		u32 rxchan, txchan;		int txid = au1xmmc_card_table[host->id].tx_devid;	int rxid = au1xmmc_card_table[host->id].rx_devid;		/* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride	   of 8 bits.  And since devices are shared, we need to create	   our own to avoid freaking out other devices	*/		int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);			txchan = au1xxx_dbdma_chan_alloc(memid, txid, 					 au1xmmc_dma_callback, (void *) host);	rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, 					 au1xmmc_dma_callback, (void *) host);	au1xxx_dbdma_set_devwidth(txchan, 8);	au1xxx_dbdma_set_devwidth(rxchan, 8);	au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);	au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);	host->tx_chan = txchan;	host->rx_chan = rxchan;}struct mmc_host_ops au1xmmc_ops = {	.request	= au1xmmc_request,	.set_ios	= au1xmmc_set_ios,};static int au1xmmc_probe(struct device *dev) {	int i, ret = 0;	/* THe interrupt is shared among all controllers */	ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0);  	if (ret) {		printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", 				AU1100_SD_IRQ, ret);		return -ENXIO;	}	disable_irq(AU1100_SD_IRQ);	for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {		struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev);		struct au1xmmc_host *host = 0;		if (!mmc) {			printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);			au1xmmc_hosts[i] = 0;			continue;		}		mmc->ops = &au1xmmc_ops;   		mmc->f_min =   450000;		mmc->f_max = 24000000;		mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;		mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; 		mmc->ocr_avail = AU1XMMC_OCR;		host = mmc_priv(mmc);		host->mmc = mmc;		host->id = i;		host->iobase = au1xmmc_card_table[host->id].iobase;		host->clock = 0;		host->power_mode = MMC_POWER_OFF;				host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;		host->status = HOST_S_IDLE;		init_timer(&host->timer);		host->timer.function = au1xmmc_poll_event;		host->timer.data = (unsigned long) host;		host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;		tasklet_init(&host->data_task, au1xmmc_tasklet_data, 				(unsigned long) host);		tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 				(unsigned long) host);		spin_lock_init(&host->lock);		if (dma != 0)			au1xmmc_init_dma(host);		au1xmmc_reset_controller(host);		mmc_add_host(mmc);		au1xmmc_hosts[i] = host;		add_timer(&host->timer);		printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",		       host->id, host->iobase, dma ? "dma" : "pio");	}  	enable_irq(AU1100_SD_IRQ);	return 0;}    static int au1xmmc_remove(struct device *dev) { 	int i;	disable_irq(AU1100_SD_IRQ);  	for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {		struct au1xmmc_host *host = au1xmmc_hosts[i];		if (!host) continue;		tasklet_kill(&host->data_task);		tasklet_kill(&host->finish_task);		del_timer_sync(&host->timer);		au1xmmc_set_power(host, 0);				mmc_remove_host(host->mmc);    		au1xxx_dbdma_chan_free(host->tx_chan);		au1xxx_dbdma_chan_free(host->rx_chan);   		au_writel(0x0, HOST_ENABLE(host));		au_sync();		} 	free_irq(AU1100_SD_IRQ, 0);	return 0;}static struct device_driver au1xmmc_driver = {	.name          = DRIVER_NAME,	.bus           = &platform_bus_type,	.probe         = au1xmmc_probe,	.remove        = au1xmmc_remove,	.suspend       = NULL,	.resume        = NULL};static int __init au1xmmc_init(void) {	return driver_register(&au1xmmc_driver);}static void __exit au1xmmc_exit(void) {	driver_unregister(&au1xmmc_driver);}module_init(au1xmmc_init);module_exit(au1xmmc_exit);#ifdef MODULEMODULE_AUTHOR("Advanced Micro Devices, Inc");MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");MODULE_LICENSE("GPL");#endif