library verilog;use verilog.vl_types.all;entity fpga_fpga_1280x8_tb is    generic(        SENDFILE01      : string  := "uart_send_data1.dat";        idle            : integer := 1;        start           : integer := 17;        write           : integer := 2;        W_and_R         : integer := 4;        write_c         : integer := 8;        clear           : integer := 0;        clear_start     : integer := 9    );end fpga_fpga_1280x8_tb;