library verilog;use verilog.vl_types.all;entity fpga_core is    generic(        idle            : integer := 1;        start           : integer := 17;        write           : integer := 2;        W_and_R         : integer := 4;        write_c         : integer := 8;        clear           : integer := 0;        clear_start     : integer := 9    );    port(        clk_54          : in     vl_logic;        clk_48          : in     vl_logic;        data_out        : out    vl_logic_vector(15 downto 0);        datain          : in     vl_logic_vector(7 downto 0);        \RESET\         : in     vl_logic;        frame_valid     : in     vl_logic;        line_valid      : in     vl_logic;        usb_flag        : in     vl_logic;        reset           : in     vl_logic    );end fpga_core;