#include "config.h"
#include "sd.h"
#include "fat.h"
void cpu_init()
{
	// Input/Output Ports initialization
	// Port A initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
	// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
	PORTA=0x00;
	DDRA=0x00;
	
	// Port B initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=Out Func1=Out Func0=Out
	// State7=T State6=T State5=T State4=T State3=T State2=0 State1=0 State0=0
	PORTB=0x01;
	DDRB=0x07;
	
	// Port C initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
	// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
	PORTC=0x00;
	DDRC=0x00;
	
	// Port D initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
	// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
	PORTD=0x00;
	DDRD=0x00;
	
	// Port E initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
	// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
	PORTE=0x00;
	DDRE=0xFF;
	
	// Port F initialization
	// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
	// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
	PORTF=0x00;
	DDRF=0x00;
	
	// Port G initialization
	// Func4=In Func3=In Func2=In Func1=In Func0=In
	// State4=T State3=T State2=T State1=T State0=T
	PORTG=0x08;
	DDRG=0xFF;
	
	// Timer/Counter 0 initialization
	// Clock source: System Clock
	// Clock value: Timer 0 Stopped
	// Mode: Normal top=FFh
	// OC0 output: Disconnected
	ASSR=0x00;
	TCCR0=0x00;
	TCNT0=0x00;
	OCR0=0x00;
	
	// Timer/Counter 1 initialization
	// Clock source: System Clock
	// Clock value: Timer 1 Stopped
	// Mode: Normal top=FFFFh
	// OC1A output: Discon.
	// OC1B output: Discon.
	// OC1C output: Discon.
	// Noise Canceler: Off
	// Input Capture on Falling Edge
	TCCR1A=0x00;
	TCCR1B=0x00;
	TCNT1H=0x00;
	TCNT1L=0x00;
	ICR1H=0x00;
	ICR1L=0x00;
	OCR1AH=0x00;
	OCR1AL=0x00;
	OCR1BH=0x00;
	OCR1BL=0x00;
	OCR1CH=0x00;
	OCR1CL=0x00;
	
	// Timer/Counter 2 initialization
	// Clock source: System Clock
	// Clock value: Timer 2 Stopped
	// Mode: Normal top=FFh
	// OC2 output: Disconnected
	TCCR2=0x00;
	TCNT2=0x00;
	OCR2=0x00;
	
	// Timer/Counter 3 initialization
	// Clock source: System Clock
	// Clock value: Timer 3 Stopped
	// Mode: Normal top=FFFFh
	// Noise Canceler: Off
	// Input Capture on Falling Edge
	// OC3A output: Discon.
	// OC3B output: Discon.
	// OC3C output: Discon.
	TCCR3A=0x00;
	TCCR3B=0x00;
	TCNT3H=0x00;
	TCNT3L=0x00;
	ICR3H=0x00;
	ICR3L=0x00;
	OCR3AH=0x00;
	OCR3AL=0x00;
	OCR3BH=0x00;
	OCR3BL=0x00;
	OCR3CH=0x00;
	OCR3CL=0x00;
	
	// External Interrupt(s) initialization
	// INT0: Off
	// INT1: Off
	// INT2: Off
	// INT3: Off
	// INT4: Off
	// INT5: Off
	// INT6: Off
	// INT7: Off
	EICRA=0x00;
	EICRB=0x00;
	EIMSK=0x00;
	
	// Timer(s)/Counter(s) Interrupt(s) initialization
	TIMSK=0x00;
	ETIMSK=0x00;
	
	// USART0 initialization
	// Communication Parameters: 8 Data, 1 Stop, No Parity
	// USART0 Receiver: On
	// USART0 Transmitter: On
	// USART0 Mode: Asynchronous
	// USART0 Baud rate: 9600
	UCSR0A=0x00;
	UCSR0B=0x18;
	UCSR0C=0x06;
	UBRR0H=0x00;
	UBRR0L=0x2F;
	
	// Analog Comparator initialization
	// Analog Comparator: Off
	// Analog Comparator Input Capture by Timer/Counter 1: Off
	ACSR=0x80;
	SFIOR=0x00;
	
	// SPI initialization
	// SPI Type: Master
	// SPI Clock Rate: 115.200 kHz
	// SPI Clock Phase: Cycle Half
	// SPI Clock Polarity: Low
	// SPI Data Order: MSB First
	SPCR=0x52;
	SPSR=0x00;
}

//8M
void delay_us(UCHAR cnt)
{
	UCHAR i;
	cnt--;
	for(i=0;i<cnt;i++)
	{
		NOP();
		NOP();
		NOP();
//		NOP();
__asm("WDR");
	}
}

void delay_ms(UCHAR cnt)
{
	UCHAR i,ii;
	for(i=0;i<cnt;i++)
	{
		for(ii=0;ii<4;ii++)
			delay_us(250);
	}

}
//-----------------------------------------------------------
void UDRT0_print(unsigned char d)
{
    UDR0=d;
    while(!(UCSR0A&(1<<6)));
    UCSR0A_Bit6=1;
}

void Debug_Pstr(const unsigned char *str)
{
	while(*str!=0)	UDRT0_print(*str++);
}

void Debug_Pdata(unsigned long data)
{
	unsigned char da[8];
	unsigned char i;
	for(i=0;i<8;i++)	da[i]=0;
	while(data>=10000000L){ ++da[7];data-=10000000L;}
	if(da[7])	i=0;
	if(i==0)	UDRT0_print('0'+da[7]);
	while(data>=1000000L) { ++da[6];data-=1000000L;}
	if(da[6])	i=0;
	if(i==0)	UDRT0_print('0'+da[6]);
	while(data>=100000L)  { ++da[5];data-=100000L;}
	if(da[5])	i=0;
	if(i==0)	UDRT0_print('0'+da[5]);
	while(data>=10000L)   { ++da[4];data-=10000L;}
	if(da[4])	i=0;
	if(i==0)	UDRT0_print('0'+da[4]);
	while(data>=1000L)    { ++da[3];data-=1000L;}
	if(da[3])	i=0;
	if(i==0)	UDRT0_print('0'+da[3]);
	while(data>=100L)     { ++da[2];data-=100L;}
	if(da[2])	i=0;
	if(i==0)	UDRT0_print('0'+da[2]);
	while(data>=10L)      { ++da[1];data-=10L;}
	if(da[1])	i=0;
	if(i==0)	UDRT0_print('0'+da[1]);
	UDRT0_print('0'+data);
}

void Debug_P16(unsigned char d)
{
	unsigned char h=(d&0xF0)>>4;
	if(h<10)	UDRT0_print('0'+h);
	else		UDRT0_print('A'-10+h);
	h=d&0x0f;
	if(h<10)	UDRT0_print('0'+h);
	else		UDRT0_print('A'-10+h);
	UDRT0_print(' ');
}

void Debug_Msg(const unsigned char *str,unsigned long data)
{
	Debug_Pstr("\n\r");Debug_Pstr(str);Debug_Pdata(data);Debug_Pstr("\n\r");
}


unsigned char getch()
{
  while(!(UCSR0A&(1<<7)));
  return UDR0;
}

unsigned char xiaoshuo_data[1024];
void print_xiaoshu()
{
	unsigned int i;
	for(i=0;i<sizeof(xiaoshuo_data);i++)	UDRT0_print(xiaoshuo_data[i]);
}

void main( void )
{
	unsigned int i;
	unsigned char fp;
    cpu_init();	
	spi_init();
	Debug_Pstr("初始化SD卡");
	for(i=0;i<10;i++)	if(SD_Init()==0)	break;
	if(i)	Debug_Pstr("Fail\n\r");
	else	Debug_Pstr("OK\n\r");
	InitFat32();
	fp=fopen("/IAR/Debug/Z.txt");
	fseek(fp,8092,0);fprtfile(fp);
	while(1)	{
		if (fread(xiaoshuo_data,sizeof(xiaoshuo_data),fp)==0 )	break;
		print_xiaoshu();
		if(getch()==0x01)	fprtfile(fp);
	}
    while(1)
    {
      PORTE^=0xFF;
      delay_ms(250);
      delay_ms(250);
    }
}