/* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $ * ultra.S: Don't expand these all over the place... * * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com) */#include <asm/asi.h>#include <asm/pgtable.h>#include <asm/page.h>#include <asm/spitfire.h>#include <asm/mmu_context.h>#include <asm/mmu.h>#include <asm/pil.h>#include <asm/head.h>#include <asm/thread_info.h>#include <asm/cacheflush.h>#include <asm/hypervisor.h>	/* Basically, most of the Spitfire vs. Cheetah madness	 * has to do with the fact that Cheetah does not support	 * IMMU flushes out of the secondary context.  Someone needs	 * to throw a south lake birthday party for the folks	 * in Microelectronics who refused to fix this shit.	 */	/* This file is meant to be read efficiently by the CPU, not humans.	 * Staraj sie tego nikomu nie pierdolnac...	 */	.text	.align		32	.globl		__flush_tlb_mm__flush_tlb_mm:		/* 18 insns */	/* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */	ldxa		[%o1] ASI_DMMU, %g2	cmp		%g2, %o0	bne,pn		%icc, __spitfire_flush_tlb_mm_slow	 mov		0x50, %g3	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	sethi		%hi(KERNBASE), %g3	flush		%g3	retl	 nop	nop	nop	nop	nop	nop	nop	nop	nop	nop	.align		32	.globl		__flush_tlb_pending__flush_tlb_pending:	/* 26 insns */	/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */	rdpr		%pstate, %g7	sllx		%o1, 3, %o1	andn		%g7, PSTATE_IE, %g2	wrpr		%g2, %pstate	mov		SECONDARY_CONTEXT, %o4	ldxa		[%o4] ASI_DMMU, %g2	stxa		%o0, [%o4] ASI_DMMU1:	sub		%o1, (1 << 3), %o1	ldx		[%o2 + %o1], %o3	andcc		%o3, 1, %g0	andn		%o3, 1, %o3	be,pn		%icc, 2f	 or		%o3, 0x10, %o3	stxa		%g0, [%o3] ASI_IMMU_DEMAP2:	stxa		%g0, [%o3] ASI_DMMU_DEMAP	membar		#Sync	brnz,pt		%o1, 1b	 nop	stxa		%g2, [%o4] ASI_DMMU	sethi		%hi(KERNBASE), %o4	flush		%o4	retl	 wrpr		%g7, 0x0, %pstate	nop	nop	nop	nop	.align		32	.globl		__flush_tlb_kernel_range__flush_tlb_kernel_range:	/* 16 insns */	/* %o0=start, %o1=end */	cmp		%o0, %o1	be,pn		%xcc, 2f	 sethi		%hi(PAGE_SIZE), %o4	sub		%o1, %o0, %o3	sub		%o3, %o4, %o3	or		%o0, 0x20, %o0		! Nucleus1:	stxa		%g0, [%o0 + %o3] ASI_DMMU_DEMAP	stxa		%g0, [%o0 + %o3] ASI_IMMU_DEMAP	membar		#Sync	brnz,pt		%o3, 1b	 sub		%o3, %o4, %o32:	sethi		%hi(KERNBASE), %o3	flush		%o3	retl	 nop	nop__spitfire_flush_tlb_mm_slow:	rdpr		%pstate, %g1	wrpr		%g1, PSTATE_IE, %pstate	stxa		%o0, [%o1] ASI_DMMU	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	flush		%g6	stxa		%g2, [%o1] ASI_DMMU	sethi		%hi(KERNBASE), %o1	flush		%o1	retl	 wrpr		%g1, 0, %pstate/* * The following code flushes one page_size worth. */	.section .kprobes.text, "ax"	.align		32	.globl		__flush_icache_page__flush_icache_page:	/* %o0 = phys_page */	membar		#StoreStore	srlx		%o0, PAGE_SHIFT, %o0	sethi		%uhi(PAGE_OFFSET), %g1	sllx		%o0, PAGE_SHIFT, %o0	sethi		%hi(PAGE_SIZE), %g2	sllx		%g1, 32, %g1	add		%o0, %g1, %o01:	subcc		%g2, 32, %g2	bne,pt		%icc, 1b	 flush		%o0 + %g2	retl	 nop#ifdef DCACHE_ALIASING_POSSIBLE#if (PAGE_SHIFT != 13)#error only page shift of 13 is supported by dcache flush#endif#define DTAG_MASK 0x3	/* This routine is Spitfire specific so the hardcoded	 * D-cache size and line-size are OK.	 */	.align		64	.globl		__flush_dcache_page__flush_dcache_page:	/* %o0=kaddr, %o1=flush_icache */	sethi		%uhi(PAGE_OFFSET), %g1	sllx		%g1, 32, %g1	sub		%o0, %g1, %o0			! physical address	srlx		%o0, 11, %o0			! make D-cache TAG	sethi		%hi(1 << 14), %o2		! D-cache size	sub		%o2, (1 << 5), %o2		! D-cache line size1:	ldxa		[%o2] ASI_DCACHE_TAG, %o3	! load D-cache TAG	andcc		%o3, DTAG_MASK, %g0		! Valid?	be,pn		%xcc, 2f			! Nope, branch	 andn		%o3, DTAG_MASK, %o3		! Clear valid bits	cmp		%o3, %o0			! TAG match?	bne,pt		%xcc, 2f			! Nope, branch	 nop	stxa		%g0, [%o2] ASI_DCACHE_TAG	! Invalidate TAG	membar		#Sync2:	brnz,pt		%o2, 1b	 sub		%o2, (1 << 5), %o2		! D-cache line size	/* The I-cache does not snoop local stores so we	 * better flush that too when necessary.	 */	brnz,pt		%o1, __flush_icache_page	 sllx		%o0, 11, %o0	retl	 nop#endif /* DCACHE_ALIASING_POSSIBLE */	.previous	/* Cheetah specific versions, patched at boot time. */__cheetah_flush_tlb_mm: /* 19 insns */	rdpr		%pstate, %g7	andn		%g7, PSTATE_IE, %g2	wrpr		%g2, 0x0, %pstate	wrpr		%g0, 1, %tl	mov		PRIMARY_CONTEXT, %o2	mov		0x40, %g3	ldxa		[%o2] ASI_DMMU, %g2	srlx		%g2, CTX_PGSZ1_NUC_SHIFT, %o1	sllx		%o1, CTX_PGSZ1_NUC_SHIFT, %o1	or		%o0, %o1, %o0	/* Preserve nucleus page size fields */	stxa		%o0, [%o2] ASI_DMMU	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	stxa		%g2, [%o2] ASI_DMMU	sethi		%hi(KERNBASE), %o2	flush		%o2	wrpr		%g0, 0, %tl	retl	 wrpr		%g7, 0x0, %pstate__cheetah_flush_tlb_pending:	/* 27 insns */	/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */	rdpr		%pstate, %g7	sllx		%o1, 3, %o1	andn		%g7, PSTATE_IE, %g2	wrpr		%g2, 0x0, %pstate	wrpr		%g0, 1, %tl	mov		PRIMARY_CONTEXT, %o4	ldxa		[%o4] ASI_DMMU, %g2	srlx		%g2, CTX_PGSZ1_NUC_SHIFT, %o3	sllx		%o3, CTX_PGSZ1_NUC_SHIFT, %o3	or		%o0, %o3, %o0	/* Preserve nucleus page size fields */	stxa		%o0, [%o4] ASI_DMMU1:	sub		%o1, (1 << 3), %o1	ldx		[%o2 + %o1], %o3	andcc		%o3, 1, %g0	be,pn		%icc, 2f	 andn		%o3, 1, %o3	stxa		%g0, [%o3] ASI_IMMU_DEMAP2:	stxa		%g0, [%o3] ASI_DMMU_DEMAP		membar		#Sync	brnz,pt		%o1, 1b	 nop	stxa		%g2, [%o4] ASI_DMMU	sethi		%hi(KERNBASE), %o4	flush		%o4	wrpr		%g0, 0, %tl	retl	 wrpr		%g7, 0x0, %pstate#ifdef DCACHE_ALIASING_POSSIBLE__cheetah_flush_dcache_page: /* 11 insns */	sethi		%uhi(PAGE_OFFSET), %g1	sllx		%g1, 32, %g1	sub		%o0, %g1, %o0	sethi		%hi(PAGE_SIZE), %o41:	subcc		%o4, (1 << 5), %o4	stxa		%g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE	membar		#Sync	bne,pt		%icc, 1b	 nop	retl		/* I-cache flush never needed on Cheetah, see callers. */	 nop#endif /* DCACHE_ALIASING_POSSIBLE */	/* Hypervisor specific versions, patched at boot time.  */__hypervisor_tlb_tl0_error:	save		%sp, -192, %sp	mov		%i0, %o0	call		hypervisor_tlbop_error	 mov		%i1, %o1	ret	 restore__hypervisor_flush_tlb_mm: /* 10 insns */	mov		%o0, %o2	/* ARG2: mmu context */	mov		0, %o0		/* ARG0: CPU lists unimplemented */	mov		0, %o1		/* ARG1: CPU lists unimplemented */	mov		HV_MMU_ALL, %o3	/* ARG3: flags */	mov		HV_FAST_MMU_DEMAP_CTX, %o5	ta		HV_FAST_TRAP	brnz,pn		%o0, __hypervisor_tlb_tl0_error	 mov		HV_FAST_MMU_DEMAP_CTX, %o1	retl	 nop__hypervisor_flush_tlb_pending: /* 16 insns */	/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */	sllx		%o1, 3, %g1	mov		%o2, %g2	mov		%o0, %g31:	sub		%g1, (1 << 3), %g1	ldx		[%g2 + %g1], %o0      /* ARG0: vaddr + IMMU-bit */	mov		%g3, %o1	      /* ARG1: mmu context */	mov		HV_MMU_ALL, %o2	      /* ARG2: flags */	srlx		%o0, PAGE_SHIFT, %o0	sllx		%o0, PAGE_SHIFT, %o0	ta		HV_MMU_UNMAP_ADDR_TRAP	brnz,pn		%o0, __hypervisor_tlb_tl0_error	 mov		HV_MMU_UNMAP_ADDR_TRAP, %o1	brnz,pt		%g1, 1b	 nop	retl	 nop__hypervisor_flush_tlb_kernel_range: /* 16 insns */	/* %o0=start, %o1=end */	cmp		%o0, %o1	be,pn		%xcc, 2f	 sethi		%hi(PAGE_SIZE), %g3	mov		%o0, %g1	sub		%o1, %g1, %g2	sub		%g2, %g3, %g21:	add		%g1, %g2, %o0	/* ARG0: virtual address */	mov		0, %o1		/* ARG1: mmu context */	mov		HV_MMU_ALL, %o2	/* ARG2: flags */	ta		HV_MMU_UNMAP_ADDR_TRAP	brnz,pn		%o0, __hypervisor_tlb_tl0_error	 mov		HV_MMU_UNMAP_ADDR_TRAP, %o1	brnz,pt		%g2, 1b	 sub		%g2, %g3, %g22:	retl	 nop#ifdef DCACHE_ALIASING_POSSIBLE	/* XXX Niagara and friends have an 8K cache, so no aliasing is	 * XXX possible, but nothing explicit in the Hypervisor API	 * XXX guarantees this.	 */__hypervisor_flush_dcache_page:	/* 2 insns */	retl	 nop#endiftlb_patch_one:1:	lduw		[%o1], %g1	stw		%g1, [%o0]	flush		%o0	subcc		%o2, 1, %o2	add		%o1, 4, %o1	bne,pt		%icc, 1b	 add		%o0, 4, %o0	retl	 nop	.globl		cheetah_patch_cachetlbopscheetah_patch_cachetlbops:	save		%sp, -128, %sp	sethi		%hi(__flush_tlb_mm), %o0	or		%o0, %lo(__flush_tlb_mm), %o0	sethi		%hi(__cheetah_flush_tlb_mm), %o1	or		%o1, %lo(__cheetah_flush_tlb_mm), %o1	call		tlb_patch_one	 mov		19, %o2	sethi		%hi(__flush_tlb_pending), %o0	or		%o0, %lo(__flush_tlb_pending), %o0	sethi		%hi(__cheetah_flush_tlb_pending), %o1	or		%o1, %lo(__cheetah_flush_tlb_pending), %o1	call		tlb_patch_one	 mov		27, %o2#ifdef DCACHE_ALIASING_POSSIBLE	sethi		%hi(__flush_dcache_page), %o0	or		%o0, %lo(__flush_dcache_page), %o0	sethi		%hi(__cheetah_flush_dcache_page), %o1	or		%o1, %lo(__cheetah_flush_dcache_page), %o1	call		tlb_patch_one	 mov		11, %o2#endif /* DCACHE_ALIASING_POSSIBLE */	ret	 restore#ifdef CONFIG_SMP	/* These are all called by the slaves of a cross call, at	 * trap level 1, with interrupts fully disabled.	 *	 * Register usage:	 *   %g5	mm->context	(all tlb flushes)	 *   %g1	address arg 1	(tlb page and range flushes)	 *   %g7	address arg 2	(tlb range flush only)	 *	 *   %g6	scratch 1	 *   %g2	scratch 2	 *   %g3	scratch 3