/* * r8169.c: RealTek 8169/8168/8101 ethernet driver. * * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> * Copyright (c) a lot of people too. Please respect their work. * * See MAINTAINERS file for support contact information. */#include <linux/module.h>#include <linux/moduleparam.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/delay.h>#include <linux/ethtool.h>#include <linux/mii.h>#include <linux/if_vlan.h>#include <linux/crc32.h>#include <linux/in.h>#include <linux/ip.h>#include <linux/tcp.h>#include <linux/init.h>#include <linux/dma-mapping.h>#include <asm/system.h>#include <asm/io.h>#include <asm/irq.h>#ifdef CONFIG_R8169_NAPI#define NAPI_SUFFIX	"-NAPI"#else#define NAPI_SUFFIX	""#endif#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX#define MODULENAME "r8169"#define PFX MODULENAME ": "#ifdef RTL8169_DEBUG#define assert(expr) \	if (!(expr)) {					\		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\		#expr,__FILE__,__FUNCTION__,__LINE__);		\	}#define dprintk(fmt, args...) \	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)#else#define assert(expr) do {} while (0)#define dprintk(fmt, args...)	do {} while (0)#endif /* RTL8169_DEBUG */#define R8169_MSG_DEFAULT \	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)#define TX_BUFFS_AVAIL(tp) \	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)#ifdef CONFIG_R8169_NAPI#define rtl8169_rx_skb			netif_receive_skb#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb#define rtl8169_rx_quota(count, quota)	min(count, quota)#else#define rtl8169_rx_skb			netif_rx#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx#define rtl8169_rx_quota(count, quota)	count#endif/* Maximum events (Rx packets, etc.) to handle at each interrupt. */static const int max_interrupt_work = 20;/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).   The RTL chips use a 64 element hash table based on the Ethernet CRC. */static const int multicast_filter_limit = 32;/* MAC address length */#define MAC_ADDR_LEN	6#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */#define R8169_REGS_SIZE		256#define R8169_NAPI_WEIGHT	64#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */#define RX_BUF_SIZE	1536	/* Rx Buffer size */#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))#define RTL8169_TX_TIMEOUT	(6*HZ)#define RTL8169_PHY_TIMEOUT	(10*HZ)/* write/read MMIO register */#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))#define RTL_R8(reg)		readb (ioaddr + (reg))#define RTL_R16(reg)		readw (ioaddr + (reg))#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))enum mac_version {	RTL_GIGA_MAC_VER_01 = 0x01, // 8169	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C	RTL_GIGA_MAC_VER_20 = 0x14  // 8168C};#define _R(NAME,MAC,MASK) \	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }static const struct {	const char *name;	u8 mac_version;	u32 RxConfigMask;	/* Clears the bits supported by this chip */} rtl_chip_info[] = {	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E};#undef _Renum cfg_version {	RTL_CFG_0 = 0x00,	RTL_CFG_1,	RTL_CFG_2};static void rtl_hw_start_8169(struct net_device *);static void rtl_hw_start_8168(struct net_device *);static void rtl_hw_start_8101(struct net_device *);static struct pci_device_id rtl8169_pci_tbl[] = {	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },	{ PCI_VENDOR_ID_LINKSYS,		0x1032,		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },	{ 0x0001,				0x8168,		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },	{0,},};MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);static int rx_copybreak = 200;static int use_dac;static struct {	u32 msg_enable;} debug = { -1 };enum rtl_registers {	MAC0		= 0,	/* Ethernet hardware address. */	MAC4		= 4,	MAR0		= 8,	/* Multicast filter. */	CounterAddrLow		= 0x10,	CounterAddrHigh		= 0x14,	TxDescStartAddrLow	= 0x20,	TxDescStartAddrHigh	= 0x24,	TxHDescStartAddrLow	= 0x28,	TxHDescStartAddrHigh	= 0x2c,	FLASH		= 0x30,	ERSR		= 0x36,	ChipCmd		= 0x37,	TxPoll		= 0x38,	IntrMask	= 0x3c,	IntrStatus	= 0x3e,	TxConfig	= 0x40,	RxConfig	= 0x44,	RxMissed	= 0x4c,	Cfg9346		= 0x50,	Config0		= 0x51,	Config1		= 0x52,	Config2		= 0x53,	Config3		= 0x54,	Config4		= 0x55,	Config5		= 0x56,	MultiIntr	= 0x5c,	PHYAR		= 0x60,	TBICSR		= 0x64,	TBI_ANAR	= 0x68,	TBI_LPAR	= 0x6a,	PHYstatus	= 0x6c,	RxMaxSize	= 0xda,	CPlusCmd	= 0xe0,	IntrMitigate	= 0xe2,	RxDescAddrLow	= 0xe4,	RxDescAddrHigh	= 0xe8,	EarlyTxThres	= 0xec,	FuncEvent	= 0xf0,	FuncEventMask	= 0xf4,	FuncPresetState	= 0xf8,	FuncForceEvent	= 0xfc,};enum rtl_register_content {	/* InterruptStatusBits */	SYSErr		= 0x8000,	PCSTimeout	= 0x4000,	SWInt		= 0x0100,	TxDescUnavail	= 0x0080,	RxFIFOOver	= 0x0040,	LinkChg		= 0x0020,	RxOverflow	= 0x0010,	TxErr		= 0x0008,	TxOK		= 0x0004,	RxErr		= 0x0002,	RxOK		= 0x0001,	/* RxStatusDesc */	RxFOVF	= (1 << 23),	RxRWT	= (1 << 22),	RxRES	= (1 << 21),	RxRUNT	= (1 << 20),	RxCRC	= (1 << 19),	/* ChipCmdBits */	CmdReset	= 0x10,	CmdRxEnb	= 0x08,	CmdTxEnb	= 0x04,	RxBufEmpty	= 0x01,	/* TXPoll register p.5 */	HPQ		= 0x80,		/* Poll cmd on the high prio queue */	NPQ		= 0x40,		/* Poll cmd on the low prio queue */	FSWInt		= 0x01,		/* Forced software interrupt */	/* Cfg9346Bits */	Cfg9346_Lock	= 0x00,	Cfg9346_Unlock	= 0xc0,	/* rx_mode_bits */	AcceptErr	= 0x20,	AcceptRunt	= 0x10,	AcceptBroadcast	= 0x08,	AcceptMulticast	= 0x04,	AcceptMyPhys	= 0x02,	AcceptAllPhys	= 0x01,	/* RxConfigBits */	RxCfgFIFOShift	= 13,	RxCfgDMAShift	=  8,	/* TxConfigBits */	TxInterFrameGapShift = 24,	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */	/* Config1 register p.24 */	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */	PMEnable	= (1 << 0),	/* Power Management Enable */	/* Config2 register p. 25 */	PCI_Clock_66MHz = 0x01,	PCI_Clock_33MHz = 0x00,	/* Config3 register p.25 */	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */	/* Config5 register p.27 */	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */	LanWake		= (1 << 1),	/* LanWake enable/disable */	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */	/* TBICSR p.28 */	TBIReset	= 0x80000000,	TBILoopback	= 0x40000000,	TBINwEnable	= 0x20000000,	TBINwRestart	= 0x10000000,	TBILinkOk	= 0x02000000,	TBINwComplete	= 0x01000000,	/* CPlusCmd p.31 */	PktCntrDisable	= (1 << 7),	// 8168	RxVlan		= (1 << 6),	RxChkSum	= (1 << 5),	PCIDAC		= (1 << 4),	PCIMulRW	= (1 << 3),	INTT_0		= 0x0000,	// 8168	INTT_1		= 0x0001,	// 8168	INTT_2		= 0x0002,	// 8168	INTT_3		= 0x0003,	// 8168	/* rtl8169_PHYstatus */	TBI_Enable	= 0x80,	TxFlowCtrl	= 0x40,	RxFlowCtrl	= 0x20,	_1000bpsF	= 0x10,	_100bps		= 0x08,	_10bps		= 0x04,	LinkStatus	= 0x02,	FullDup		= 0x01,	/* _TBICSRBit */	TBILinkOK	= 0x02000000,	/* DumpCounterCommand */	CounterDump	= 0x8,};enum desc_status_bit {	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */	RingEnd		= (1 << 30), /* End of descriptor ring */	FirstFrag	= (1 << 29), /* First segment of a packet */	LastFrag	= (1 << 28), /* Final segment of a packet */	/* Tx private */	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */	MSSShift	= 16,        /* MSS value position */	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */	IPCS		= (1 << 18), /* Calculate IP checksum */	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */	TxVlanTag	= (1 << 17), /* Add VLAN tag */	/* Rx private */	PID1		= (1 << 18), /* Protocol ID bit 1/2 */	PID0		= (1 << 17), /* Protocol ID bit 2/2 */#define RxProtoUDP	(PID1)#define RxProtoTCP	(PID0)#define RxProtoIP	(PID1 | PID0)#define RxProtoMask	RxProtoIP	IPFail		= (1 << 16), /* IP checksum failed */	UDPFail		= (1 << 15), /* UDP/IP checksum failed */	TCPFail		= (1 << 14), /* TCP/IP checksum failed */	RxVlanTag	= (1 << 16), /* VLAN tag available */};#define RsvdMask	0x3fffc000struct TxDesc {	__le32 opts1;	__le32 opts2;	__le64 addr;};struct RxDesc {	__le32 opts1;	__le32 opts2;	__le64 addr;};struct ring_info {	struct sk_buff	*skb;	u32		len;	u8		__pad[sizeof(void *) - sizeof(u32)];};enum features {	RTL_FEATURE_WOL	= (1 << 0),	RTL_FEATURE_MSI	= (1 << 1),};struct rtl8169_private {	void __iomem *mmio_addr;	/* memory map physical address */	struct pci_dev *pci_dev;	/* Index of PCI device */	struct net_device *dev;#ifdef CONFIG_R8169_NAPI	struct napi_struct napi;#endif	spinlock_t lock;		/* spin lock flag */	u32 msg_enable;	int chipset;	int mac_version;	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */	u32 dirty_rx;	u32 dirty_tx;	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */	dma_addr_t TxPhyAddr;	dma_addr_t RxPhyAddr;	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */	unsigned align;	unsigned rx_buf_sz;	struct timer_list timer;	u16 cp_cmd;	u16 intr_event;	u16 napi_event;	u16 intr_mask;	int phy_auto_nego_reg;	int phy_1000_ctrl_reg;#ifdef CONFIG_R8169_VLAN	struct vlan_group *vlgrp;#endif	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);	void (*get_settings)(struct net_device *, struct ethtool_cmd *);	void (*phy_reset_enable)(void __iomem *);	void (*hw_start)(struct net_device *);	unsigned int (*phy_reset_pending)(void __iomem *);	unsigned int (*link_ok)(void __iomem *);	struct delayed_work task;	unsigned features;};MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");module_param(rx_copybreak, int, 0);MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");module_param(use_dac, int, 0);MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");module_param_named(debug, debug.msg_enable, int, 0);MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");MODULE_LICENSE("GPL");MODULE_VERSION(RTL8169_VERSION);static int rtl8169_open(struct net_device *dev);static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);static int rtl8169_init_ring(struct net_device *dev);static void rtl_hw_start(struct net_device *dev);static int rtl8169_close(struct net_device *dev);static void rtl_set_rx_mode(struct net_device *dev);static void rtl8169_tx_timeout(struct net_device *dev);static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,				void __iomem *, u32 budget);static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);static void rtl8169_down(struct net_device *dev);static void rtl8169_rx_clear(struct rtl8169_private *tp);#ifdef CONFIG_R8169_NAPIstatic int rtl8169_poll(struct napi_struct *napi, int budget);#endifstatic const unsigned int rtl8169_rx_config =	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);static void mdio_write(void __iomem *ioaddr, int reg_addr, int value){	int i;	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));	for (i = 20; i > 0; i--) {		/*		 * Check if the RTL8169 has completed writing to the specified		 * MII register.		 */		if (!(RTL_R32(PHYAR) & 0x80000000))			break;		udelay(25);	}}static int mdio_read(void __iomem *ioaddr, int reg_addr){	int i, value = -1;	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);	for (i = 20; i > 0; i--) {		/*		 * Check if the RTL8169 has completed retrieving data from		 * the specified MII register.		 */		if (RTL_R32(PHYAR) & 0x80000000) {			value = RTL_R32(PHYAR) & 0xffff;			break;		}		udelay(25);	}	return value;}static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr){	RTL_W16(IntrMask, 0x0000);	RTL_W16(IntrStatus, 0xffff);}static void rtl8169_asic_down(void __iomem *ioaddr){