#define IXGBE_PAP       0x04248#define IXGBE_MACA      0x0424C#define IXGBE_APAE      0x04250#define IXGBE_ARD       0x04254#define IXGBE_AIS       0x04258#define IXGBE_MSCA      0x0425C#define IXGBE_MSRWD     0x04260#define IXGBE_MLADD     0x04264#define IXGBE_MHADD     0x04268#define IXGBE_TREG      0x0426C#define IXGBE_PCSS1     0x04288#define IXGBE_PCSS2     0x0428C#define IXGBE_XPCSS     0x04290#define IXGBE_SERDESC   0x04298#define IXGBE_MACS      0x0429C#define IXGBE_AUTOC     0x042A0#define IXGBE_LINKS     0x042A4#define IXGBE_AUTOC2    0x042A8#define IXGBE_AUTOC3    0x042AC#define IXGBE_ANLP1     0x042B0#define IXGBE_ANLP2     0x042B4#define IXGBE_ATLASCTL  0x04800/* RSCCTL Bit Masks */#define IXGBE_RSCCTL_RSCEN          0x01#define IXGBE_RSCCTL_MAXDESC_1      0x00#define IXGBE_RSCCTL_MAXDESC_4      0x04#define IXGBE_RSCCTL_MAXDESC_8      0x08#define IXGBE_RSCCTL_MAXDESC_16     0x0C/* CTRL Bit Masks */#define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */#define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */#define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) *//* FACTPS */#define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select *//* MHADD Bit Masks */#define IXGBE_MHADD_MFS_MASK    0xFFFF0000#define IXGBE_MHADD_MFS_SHIFT   16/* Extended Device Control */#define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */#define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW *//* Direct Cache Access (DCA) definitions */#define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */#define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues *//* MSCA Bit Masks */#define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */#define IXGBE_MSCA_NP_ADDR_SHIFT     0#define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */#define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */#define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */#define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/#define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */#define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */#define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */#define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */#define IXGBE_MSCA_READ              0x08000000 /* OP CODE 10 (read) */#define IXGBE_MSCA_READ_AUTOINC      0x0C000000 /* OP CODE 11 (read, auto inc)*/#define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */#define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */#define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */#define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */#define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */#define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable *//* MSRWD bit masks */#define IXGBE_MSRWD_WRITE_DATA_MASK  0x0000FFFF#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0#define IXGBE_MSRWD_READ_DATA_MASK   0xFFFF0000#define IXGBE_MSRWD_READ_DATA_SHIFT  16/* Atlas registers */#define IXGBE_ATLAS_PDN_LPBK    0x24#define IXGBE_ATLAS_PDN_10G     0xB#define IXGBE_ATLAS_PDN_1G      0xC#define IXGBE_ATLAS_PDN_AN      0xD/* Atlas bit masks */#define IXGBE_ATLASCTL_WRITE_CMD        0x00010000#define IXGBE_ATLAS_PDN_TX_REG_EN       0x10#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0/* Device Type definitions for new protocol MDIO commands */#define IXGBE_MDIO_PMA_PMD_DEV_TYPE               0x1#define IXGBE_MDIO_PCS_DEV_TYPE                   0x3#define IXGBE_MDIO_PHY_XS_DEV_TYPE                0x4#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE              0x7#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE     0x1E   /* Device 30 */#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010#define IXGBE_MDIO_AUTO_NEG_CONTROL    0x0 /* AUTO_NEG Control Reg */#define IXGBE_MDIO_AUTO_NEG_STATUS     0x1 /* AUTO_NEG Status Reg */#define IXGBE_MDIO_PHY_XS_CONTROL      0x0 /* PHY_XS Control Reg */#define IXGBE_MDIO_PHY_XS_RESET        0x8000 /* PHY_XS Reset */#define IXGBE_MDIO_PHY_ID_HIGH         0x2 /* PHY ID High Reg*/#define IXGBE_MDIO_PHY_ID_LOW          0x3 /* PHY ID Low Reg*/#define IXGBE_MDIO_PHY_SPEED_ABILITY   0x4 /* Speed Abilty Reg */#define IXGBE_MDIO_PHY_SPEED_10G       0x0001 /* 10G capable */#define IXGBE_MDIO_PHY_SPEED_1G        0x0010 /* 1G capable */#define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0#define IXGBE_MAX_PHY_ADDR             32/* PHY IDs*/#define TN1010_PHY_ID    0x00A19410#define QT2022_PHY_ID    0x0043A400/* General purpose Interrupt Enable */#define IXGBE_GPIE_MSIX_MODE      0x00000010 /* MSI-X mode */#define IXGBE_GPIE_OCD            0x00000020 /* Other Clear Disable */#define IXGBE_GPIE_EIMEN          0x00000040 /* Immediate Interrupt Enable */#define IXGBE_GPIE_EIAME          0x40000000#define IXGBE_GPIE_PBA_SUPPORT    0x80000000/* Transmit Flow Control status */#define IXGBE_TFCS_TXOFF         0x00000001#define IXGBE_TFCS_TXOFF0        0x00000100#define IXGBE_TFCS_TXOFF1        0x00000200#define IXGBE_TFCS_TXOFF2        0x00000400#define IXGBE_TFCS_TXOFF3        0x00000800#define IXGBE_TFCS_TXOFF4        0x00001000#define IXGBE_TFCS_TXOFF5        0x00002000#define IXGBE_TFCS_TXOFF6        0x00004000#define IXGBE_TFCS_TXOFF7        0x00008000/* TCP Timer */#define IXGBE_TCPTIMER_KS            0x00000100#define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200#define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400#define IXGBE_TCPTIMER_LOOP          0x00000800#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF/* HLREG0 Bit Masks */#define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */#define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */#define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */#define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */#define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */#define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */#define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */#define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */#define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */#define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */#define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */#define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 *//* VMD_CTL bitmasks */#define IXGBE_VMD_CTL_VMDQ_EN     0x00000001#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002/* RDHMPN and TDHMPN bitmasks */#define IXGBE_RDHMPN_RDICADDR       0x007FF800#define IXGBE_RDHMPN_RDICRDREQ      0x00800000#define IXGBE_RDHMPN_RDICADDR_SHIFT 11#define IXGBE_TDHMPN_TDICADDR       0x003FF800#define IXGBE_TDHMPN_TDICRDREQ      0x00800000#define IXGBE_TDHMPN_TDICADDR_SHIFT 11/* Receive Checksum Control */#define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */#define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled *//* FCRTL Bit Masks */#define IXGBE_FCRTL_XONE        0x80000000  /* bit 31, XON enable */#define IXGBE_FCRTH_FCEN        0x80000000  /* Rx Flow control enable *//* PAP bit masks*/#define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask *//* RMCS Bit Masks */#define IXGBE_RMCS_RRM          0x00000002 /* Receive Recylce Mode enable *//* Receive Arbitration Control: 0 Round Robin, 1 DFP */#define IXGBE_RMCS_RAC          0x00000004#define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */#define IXGBE_RMCS_TFCE_802_3X  0x00000008 /* Tx Priority flow control ena */#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */#define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit *//* Interrupt register bitmasks *//* Extended Interrupt Cause Read */#define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */#define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */#define IXGBE_EICR_MNG          0x00400000 /* Managability Event Interrupt */#define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */#define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */#define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */#define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active *//* Extended Interrupt Cause Set */#define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */#define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */#define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */#define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */#define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Error */#define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */#define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */#define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active *//* Extended Interrupt Mask Set */#define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */#define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */#define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */#define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Error */#define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */#define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */#define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active *//* Extended Interrupt Mask Clear */#define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */#define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */#define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */#define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Error */#define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */#define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */#define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */#define IXGBE_EIMS_ENABLE_MASK (\				IXGBE_EIMS_RTX_QUEUE       | \				IXGBE_EIMS_LSC             | \				IXGBE_EIMS_TCP_TIMER       | \				IXGBE_EIMS_OTHER)/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */#define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */#define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */#define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */#define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */#define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */#define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */#define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */#define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */#define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */#define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits *//* Interrupt clear mask */#define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF/* Interrupt Vector Allocation Registers */#define IXGBE_IVAR_REG_NUM      25#define IXGBE_IVAR_TXRX_ENTRY   96#define IXGBE_IVAR_RX_ENTRY     64#define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))#define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))#define IXGBE_IVAR_TX_ENTRY     32#define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */#define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */#define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))#define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid *//* VLAN Control Bit Masks */#define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */#define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */#define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */#define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */#define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol *//* STATUS Bit Masks */#define IXGBE_STATUS_LAN_ID     0x0000000C /* LAN ID */#define IXGBE_STATUS_GIO        0x00080000 /* GIO Master Enable Status */#define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */#define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 *//* ESDP Bit Masks */#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */#define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */#define IXGBE_ESDP_SDP5_DIR     0x00000008 /* SDP5 IO direction *//* LEDCTL Bit Masks */#define IXGBE_LED_IVRT_BASE      0x00000040#define IXGBE_LED_BLINK_BASE     0x00000080#define IXGBE_LED_MODE_MASK_BASE 0x0000000F#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))#define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)#define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)#define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)/* LED modes */#define IXGBE_LED_LINK_UP       0x0#define IXGBE_LED_LINK_10G      0x1#define IXGBE_LED_MAC           0x2#define IXGBE_LED_FILTER        0x3#define IXGBE_LED_LINK_ACTIVE   0x4#define IXGBE_LED_LINK_1G       0x5#define IXGBE_LED_ON            0xE#define IXGBE_LED_OFF           0xF/* AUTOC Bit Masks */#define IXGBE_AUTOC_KX4_SUPP    0x80000000#define IXGBE_AUTOC_KX_SUPP     0x40000000#define IXGBE_AUTOC_PAUSE       0x30000000#define IXGBE_AUTOC_RF          0x08000000#define IXGBE_AUTOC_PD_TMR      0x06000000#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000