#define IXGBE_AUTOC_AN_RESTART  0x00001000#define IXGBE_AUTOC_FLU         0x00000001#define IXGBE_AUTOC_LMS_SHIFT   13#define IXGBE_AUTOC_LMS_MASK   (0x7 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN  (0x0 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_1G_AN  (0x2 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN   (0x6 << IXGBE_AUTOC_LMS_SHIFT)#define IXGBE_AUTOC_LMS_ATTACH_TYPE    (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)#define IXGBE_AUTOC_1G_PMA_PMD      0x00000200#define IXGBE_AUTOC_10G_PMA_PMD     0x00000180#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9#define IXGBE_AUTOC_10G_XAUI   (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)#define IXGBE_AUTOC_10G_KX4    (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)#define IXGBE_AUTOC_10G_CX4    (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)#define IXGBE_AUTOC_1G_BX      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)#define IXGBE_AUTOC_1G_KX      (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)/* LINKS Bit Masks */#define IXGBE_LINKS_KX_AN_COMP  0x80000000#define IXGBE_LINKS_UP          0x40000000#define IXGBE_LINKS_SPEED       0x20000000#define IXGBE_LINKS_MODE        0x18000000#define IXGBE_LINKS_RX_MODE     0x06000000#define IXGBE_LINKS_TX_MODE     0x01800000#define IXGBE_LINKS_XGXS_EN     0x00400000#define IXGBE_LINKS_PCS_1G_EN   0x00200000#define IXGBE_LINKS_1G_AN_EN    0x00100000#define IXGBE_LINKS_KX_AN_IDLE  0x00080000#define IXGBE_LINKS_1G_SYNC     0x00040000#define IXGBE_LINKS_10G_ALIGN   0x00020000#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000#define IXGBE_LINKS_TL_FAULT    0x00001000#define IXGBE_LINKS_SIGNAL      0x00000F00#define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds *//* SW Semaphore Register bitmasks */#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock *//* GSSR definitions */#define IXGBE_GSSR_EEP_SM     0x0001#define IXGBE_GSSR_PHY0_SM    0x0002#define IXGBE_GSSR_PHY1_SM    0x0004#define IXGBE_GSSR_MAC_CSR_SM 0x0008#define IXGBE_GSSR_FLASH_SM   0x0010/* EEC Register */#define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */#define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */#define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */#define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */#define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */#define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */#define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */#define IXGBE_EEC_FWE_SHIFT 4#define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */#define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */#define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */#define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done *//* EEPROM Addressing bits based on type (0-small, 1-large) */#define IXGBE_EEC_ADDR_SIZE 0x00000400#define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */#define IXGBE_EEC_SIZE_SHIFT          11#define IXGBE_EEPROM_WORD_SIZE_SHIFT  6#define IXGBE_EEPROM_OPCODE_BITS      8/* Checksum and EEPROM pointers */#define IXGBE_EEPROM_CHECKSUM   0x3F#define IXGBE_EEPROM_SUM        0xBABA#define IXGBE_PCIE_ANALOG_PTR   0x03#define IXGBE_ATLAS0_CONFIG_PTR 0x04#define IXGBE_ATLAS1_CONFIG_PTR 0x05#define IXGBE_PCIE_GENERAL_PTR  0x06#define IXGBE_PCIE_CONFIG0_PTR  0x07#define IXGBE_PCIE_CONFIG1_PTR  0x08#define IXGBE_CORE0_PTR         0x09#define IXGBE_CORE1_PTR         0x0A#define IXGBE_MAC0_PTR          0x0B#define IXGBE_MAC1_PTR          0x0C#define IXGBE_CSR0_CONFIG_PTR   0x0D#define IXGBE_CSR1_CONFIG_PTR   0x0E#define IXGBE_FW_PTR            0x0F#define IXGBE_PBANUM0_PTR       0x15#define IXGBE_PBANUM1_PTR       0x16/* EEPROM Commands - SPI */#define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */#define IXGBE_EEPROM_STATUS_RDY_SPI     0x01#define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */#define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */#define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */#define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch *//* EEPROM reset Write Enbale latch */#define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04#define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */#define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */#define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B *//* EEPROM Read Register */#define IXGBE_EEPROM_READ_REG_DATA   16   /* data offset in EEPROM read reg */#define IXGBE_EEPROM_READ_REG_DONE   2    /* Offset to READ done bit */#define IXGBE_EEPROM_READ_REG_START  1    /* First bit to start operation */#define IXGBE_EEPROM_READ_ADDR_SHIFT 2    /* Shift to the address bits */#define IXGBE_ETH_LENGTH_OF_ADDRESS   6#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */#endif#ifndef IXGBE_EERD_ATTEMPTS/* Number of 5 microseconds we wait for EERD read to complete */#define IXGBE_EERD_ATTEMPTS 100000#endif/* PCI Bus Info */#define IXGBE_PCI_LINK_STATUS     0xB2#define IXGBE_PCI_LINK_WIDTH      0x3F0#define IXGBE_PCI_LINK_WIDTH_1    0x10#define IXGBE_PCI_LINK_WIDTH_2    0x20#define IXGBE_PCI_LINK_WIDTH_4    0x40#define IXGBE_PCI_LINK_WIDTH_8    0x80#define IXGBE_PCI_LINK_SPEED      0xF#define IXGBE_PCI_LINK_SPEED_2500 0x1#define IXGBE_PCI_LINK_SPEED_5000 0x2/* Number of 100 microseconds we wait for PCI Express master disable */#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800/* PHY Types */#define IXGBE_M88E1145_E_PHY_ID  0x01410CD0/* Check whether address is multicast.  This is little-endian specific check.*/#define IXGBE_IS_MULTICAST(Address) \		(bool)(((u8 *)(Address))[0] & ((u8)0x01))/* Check whether an address is broadcast. */#define IXGBE_IS_BROADCAST(Address)                      \		((((u8 *)(Address))[0] == ((u8)0xff)) && \		(((u8 *)(Address))[1] == ((u8)0xff)))/* RAH */#define IXGBE_RAH_VIND_MASK     0x003C0000#define IXGBE_RAH_VIND_SHIFT    18#define IXGBE_RAH_AV            0x80000000/* Filters */#define IXGBE_MC_TBL_SIZE       128  /* Multicast Filter Table (4096 bits) */#define IXGBE_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) *//* Header split receive */#define IXGBE_RFCTL_ISCSI_DIS       0x00000001#define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1#define IXGBE_RFCTL_NFSW_DIS        0x00000040#define IXGBE_RFCTL_NFSR_DIS        0x00000080#define IXGBE_RFCTL_NFS_VER_MASK    0x00000300#define IXGBE_RFCTL_NFS_VER_SHIFT   8#define IXGBE_RFCTL_NFS_VER_2       0#define IXGBE_RFCTL_NFS_VER_3       1#define IXGBE_RFCTL_NFS_VER_4       2#define IXGBE_RFCTL_IPV6_DIS        0x00000400#define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800#define IXGBE_RFCTL_IPFRSP_DIS      0x00004000#define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000/* Transmit Config masks */#define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */#define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing *//* Enable short packet padding to 64 bytes */#define IXGBE_TX_PAD_ENABLE     0x00000400#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames *//* This allows for 16K packets + 4k for vlan */#define IXGBE_MAX_FRAME_SZ      0x40040000#define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq. # write-back enable *//* Receive Config masks */#define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */#define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */#define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame *//* Receive Priority Flow Control Enbale */#define IXGBE_FCTRL_RPFCE 0x00004000#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena *//* Multiple Receive Queue Control */#define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */#define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000#define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000#define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000#define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000#define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */#define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */#define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */#define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */#define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */#define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */#define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */#define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */#define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done *//* Receive Descriptor bit definitions */#define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */#define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */#define IXGBE_RXD_STAT_IXSM     0x04    /* Ignore checksum */#define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */#define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */#define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */#define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */#define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */#define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */#define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */#define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */#define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */#define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */#define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */#define IXGBE_RXD_ERR_LE        0x02    /* Length Error */#define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */#define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */#define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */#define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */#define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */#define IXGBE_RXDADV_HBO        0x00800000#define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */#define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */#define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */#define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */#define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */#define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */#define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */#define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */#define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */#define IXGBE_RXD_PRI_SHIFT     13#define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */#define IXGBE_RXD_CFI_SHIFT     12/* SRRCTL bit definitions */#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10     /* so many KBs */#define IXGBE_SRRCTL_BSIZEPKT_MASK  0x0000007F#define IXGBE_SRRCTL_BSIZEHDR_MASK  0x00003F00#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000#define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF#define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F#define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0#define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0#define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5#define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000#define IXGBE_RXDADV_SPH                0x8000/* RSS Hash results */#define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001#define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003#define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004#define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009/* RSS Packet Types as indicated in the receive descriptor. */#define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000#define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */#define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */#define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */#define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */#define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */#define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */#define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */#define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present *//* Masks to determine if packets should be dropped due to frame errors */#define IXGBE_RXD_ERR_FRAME_ERR_MASK (\				      IXGBE_RXD_ERR_CE | \				      IXGBE_RXD_ERR_LE | \				      IXGBE_RXD_ERR_PE | \				      IXGBE_RXD_ERR_OSE | \				      IXGBE_RXD_ERR_USE)#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK (\				      IXGBE_RXDADV_ERR_CE | \				      IXGBE_RXDADV_ERR_LE | \				      IXGBE_RXDADV_ERR_PE | \				      IXGBE_RXDADV_ERR_OSE | \				      IXGBE_RXDADV_ERR_USE)/* Multicast bit mask */#define IXGBE_MCSTCTRL_MFE      0x4/* Number of Transmit and Receive Descriptors must be a multiple of 8 */#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8#define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024/* Vlan-specific macros */#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */#define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT/* Transmit Descriptor - Legacy */