struct ixgbe_legacy_tx_desc {	u64 buffer_addr;       /* Address of the descriptor's data buffer */	union {		u32 data;		struct {			u16 length;    /* Data buffer length */			u8 cso; /* Checksum offset */			u8 cmd; /* Descriptor control */		} flags;	} lower;	union {		u32 data;		struct {			u8 status;     /* Descriptor status */			u8 css; /* Checksum start */			u16 vlan;		} fields;	} upper;};/* Transmit Descriptor - Advanced */union ixgbe_adv_tx_desc {	struct {		u64 buffer_addr;       /* Address of descriptor's data buf */		u32 cmd_type_len;		u32 olinfo_status;	} read;	struct {		u64 rsvd;       /* Reserved */		u32 nxtseq_seed;		u32 status;	} wb;};/* Receive Descriptor - Legacy */struct ixgbe_legacy_rx_desc {	u64 buffer_addr; /* Address of the descriptor's data buffer */	u16 length;      /* Length of data DMAed into data buffer */	u16 csum;        /* Packet checksum */	u8 status;       /* Descriptor status */	u8 errors;       /* Descriptor Errors */	u16 vlan;};/* Receive Descriptor - Advanced */union ixgbe_adv_rx_desc {	struct {		u64 pkt_addr; /* Packet buffer address */		u64 hdr_addr; /* Header buffer address */	} read;	struct {		struct {			struct {				u16 pkt_info; /* RSS type, Packet type */				u16 hdr_info; /* Split Header, header len */			} lo_dword;			union {				u32 rss; /* RSS Hash */				struct {					u16 ip_id; /* IP id */					u16 csum; /* Packet Checksum */				} csum_ip;			} hi_dword;		} lower;		struct {			u32 status_error; /* ext status/error */			u16 length; /* Packet length */			u16 vlan; /* VLAN tag */		} upper;	} wb;  /* writeback */};/* Context descriptors */struct ixgbe_adv_tx_context_desc {	u32 vlan_macip_lens;	u32 seqnum_seed;	u32 type_tucmd_mlhl;	u32 mss_l4len_idx;};/* Adv Transmit Descriptor Config Masks */#define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buffer length(bytes) */#define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */#define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */#define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */#define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */#define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */#define IXGBE_ADVTXD_DCMD_RDMA  0x04000000 /* RDMA */#define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000     /* DDP hdr type or iSCSI */#define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */#define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */#define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */#define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */#define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED present in WB */#define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */#define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */#define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \				IXGBE_ADVTXD_POPTS_SHIFT)#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \				IXGBE_ADVTXD_POPTS_SHIFT)#define IXGBE_ADVTXD_POPTS_EOM  0x00000400 /* Enable L bit-RDMA DDP hdr */#define IXGBE_ADVTXD_POPTS_ISCO_1ST   0x00000000 /* 1st TSO of iSCSI PDU */#define IXGBE_ADVTXD_POPTS_ISCO_MDL   0x00000800 /* Middle TSO of iSCSI PDU */#define IXGBE_ADVTXD_POPTS_ISCO_LAST  0x00001000 /* Last TSO of iSCSI PDU */#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/#define IXGBE_ADVTXD_POPTS_RSV  0x00002000 /* POPTS Reserved */#define IXGBE_ADVTXD_PAYLEN_SHIFT  14 /* Adv desc PAYLEN shift */#define IXGBE_ADVTXD_MACLEN_SHIFT  9  /* Adv ctxt desc mac len shift */#define IXGBE_ADVTXD_VLAN_SHIFT    16  /* Adv ctxt vlan tag shift */#define IXGBE_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */#define IXGBE_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */#define IXGBE_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */#define IXGBE_ADVTXD_L4LEN_SHIFT   8  /* Adv ctxt L4LEN shift */#define IXGBE_ADVTXD_MSS_SHIFT     16  /* Adv ctxt MSS shift *//* Link speed */#define IXGBE_LINK_SPEED_UNKNOWN   0#define IXGBE_LINK_SPEED_100_FULL  0x0008#define IXGBE_LINK_SPEED_1GB_FULL  0x0020#define IXGBE_LINK_SPEED_10GB_FULL 0x0080enum ixgbe_eeprom_type {	ixgbe_eeprom_uninitialized = 0,	ixgbe_eeprom_spi,	ixgbe_eeprom_none /* No NVM support */};enum ixgbe_mac_type {	ixgbe_mac_unknown = 0,	ixgbe_mac_82598EB,	ixgbe_num_macs};enum ixgbe_phy_type {	ixgbe_phy_unknown = 0,	ixgbe_phy_tn,	ixgbe_phy_qt,	ixgbe_phy_xaui};enum ixgbe_media_type {	ixgbe_media_type_unknown = 0,	ixgbe_media_type_fiber,	ixgbe_media_type_copper,	ixgbe_media_type_backplane};/* Flow Control Settings */enum ixgbe_fc_type {	ixgbe_fc_none = 0,	ixgbe_fc_rx_pause,	ixgbe_fc_tx_pause,	ixgbe_fc_full,	ixgbe_fc_default};struct ixgbe_addr_filter_info {	u32 num_mc_addrs;	u32 rar_used_count;	u32 mc_addr_in_rar_count;	u32 mta_in_use;};/* Flow control parameters */struct ixgbe_fc_info {	u32 high_water; /* Flow Control High-water */	u32 low_water; /* Flow Control Low-water */	u16 pause_time; /* Flow Control Pause timer */	bool send_xon; /* Flow control send XON */	bool strict_ieee; /* Strict IEEE mode */	enum ixgbe_fc_type type; /* Type of flow control */	enum ixgbe_fc_type original_type;};/* Statistics counters collected by the MAC */struct ixgbe_hw_stats {	u64 crcerrs;	u64 illerrc;	u64 errbc;	u64 mspdc;	u64 mpctotal;	u64 mpc[8];	u64 mlfc;	u64 mrfc;	u64 rlec;	u64 lxontxc;	u64 lxonrxc;	u64 lxofftxc;	u64 lxoffrxc;	u64 pxontxc[8];	u64 pxonrxc[8];	u64 pxofftxc[8];	u64 pxoffrxc[8];	u64 prc64;	u64 prc127;	u64 prc255;	u64 prc511;	u64 prc1023;	u64 prc1522;	u64 gprc;	u64 bprc;	u64 mprc;	u64 gptc;	u64 gorc;	u64 gotc;	u64 rnbc[8];	u64 ruc;	u64 rfc;	u64 roc;	u64 rjc;	u64 mngprc;	u64 mngpdc;	u64 mngptc;	u64 tor;	u64 tpr;	u64 tpt;	u64 ptc64;	u64 ptc127;	u64 ptc255;	u64 ptc511;	u64 ptc1023;	u64 ptc1522;	u64 mptc;	u64 bptc;	u64 xec;	u64 rqsmr[16];	u64 tqsmr[8];	u64 qprc[16];	u64 qptc[16];	u64 qbrc[16];	u64 qbtc[16];};/* forward declaration */struct ixgbe_hw;struct ixgbe_mac_operations {	s32 (*reset)(struct ixgbe_hw *);	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);};struct ixgbe_phy_operations {	s32 (*setup)(struct ixgbe_hw *);	s32 (*check)(struct ixgbe_hw *, u32 *, bool *);	s32 (*setup_speed)(struct ixgbe_hw *, u32, bool, bool);	s32 (*get_settings)(struct ixgbe_hw *, u32 *, bool *);};struct ixgbe_mac_info {	struct ixgbe_mac_operations	ops;	enum ixgbe_mac_type		type;	u8				addr[IXGBE_ETH_LENGTH_OF_ADDRESS];	u8				perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];	s32				mc_filter_type;	u32				num_rx_queues;	u32				num_tx_queues;	u32				num_rx_addrs;	u32				link_attach_type;	u32				link_mode_select;	bool				link_settings_loaded;};struct ixgbe_eeprom_info {	enum ixgbe_eeprom_type		type;	u16				word_size;	u16				address_bits;};struct ixgbe_phy_info {	struct ixgbe_phy_operations	ops;	enum ixgbe_phy_type		type;	u32				addr;	u32				id;	u32				revision;	enum ixgbe_media_type		media_type;	u32				autoneg_advertised;	bool				autoneg_wait_to_complete;};struct ixgbe_info {	enum ixgbe_mac_type		mac;	s32 				(*get_invariants)(struct ixgbe_hw *);	struct ixgbe_mac_operations	*mac_ops;	struct ixgbe_phy_operations	*phy_ops;};struct ixgbe_hw {	u8 __iomem			*hw_addr;	void				*back;	struct ixgbe_mac_info		mac;	struct ixgbe_addr_filter_info	addr_ctrl;	struct ixgbe_fc_info		fc;	struct ixgbe_phy_info		phy;	struct ixgbe_eeprom_info	eeprom;	u16				device_id;	u16				vendor_id;	u16				subsystem_device_id;	u16				subsystem_vendor_id;	u8				revision_id;	bool				adapter_stopped;};/* Error Codes */#define IXGBE_ERR_EEPROM                        -1#define IXGBE_ERR_EEPROM_CHECKSUM               -2#define IXGBE_ERR_PHY                           -3#define IXGBE_ERR_CONFIG                        -4#define IXGBE_ERR_PARAM                         -5#define IXGBE_ERR_MAC_TYPE                      -6#define IXGBE_ERR_UNKNOWN_PHY                   -7#define IXGBE_ERR_LINK_SETUP                    -8#define IXGBE_ERR_ADAPTER_STOPPED               -9#define IXGBE_ERR_INVALID_MAC_ADDR              -10#define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11#define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12#define IXGBE_ERR_INVALID_LINK_SETTINGS         -13#define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14#define IXGBE_ERR_RESET_FAILED                  -15#define IXGBE_ERR_SWFW_SYNC                     -16#define IXGBE_ERR_PHY_ADDR_INVALID              -17#define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF#endif /* _IXGBE_TYPE_H_ */