/*******************************************************************************  Intel 10 Gigabit PCI Express Linux driver  Copyright(c) 1999 - 2007 Intel Corporation.  This program is free software; you can redistribute it and/or modify it  under the terms and conditions of the GNU General Public License,  version 2, as published by the Free Software Foundation.  This program is distributed in the hope it will be useful, but WITHOUT  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for  more details.  You should have received a copy of the GNU General Public License along with  this program; if not, write to the Free Software Foundation, Inc.,  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.  The full GNU General Public License is included in this distribution in  the file called "COPYING".  Contact Information:  Linux NICS <linux.nics@intel.com>  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497*******************************************************************************//* ethtool support for ixgbe */#include <linux/types.h>#include <linux/module.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/ethtool.h>#include <linux/vmalloc.h>#include <linux/uaccess.h>#include "ixgbe.h"#define IXGBE_ALL_RAR_ENTRIES 16struct ixgbe_stats {	char stat_string[ETH_GSTRING_LEN];	int sizeof_stat;	int stat_offset;};#define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \		      offsetof(struct ixgbe_adapter, m)static struct ixgbe_stats ixgbe_gstrings_stats[] = {	{"rx_packets", IXGBE_STAT(net_stats.rx_packets)},	{"tx_packets", IXGBE_STAT(net_stats.tx_packets)},	{"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},	{"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},	{"lsc_int", IXGBE_STAT(lsc_int)},	{"tx_busy", IXGBE_STAT(tx_busy)},	{"non_eop_descs", IXGBE_STAT(non_eop_descs)},	{"rx_errors", IXGBE_STAT(net_stats.rx_errors)},	{"tx_errors", IXGBE_STAT(net_stats.tx_errors)},	{"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},	{"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},	{"multicast", IXGBE_STAT(net_stats.multicast)},	{"broadcast", IXGBE_STAT(stats.bprc)},	{"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },	{"collisions", IXGBE_STAT(net_stats.collisions)},	{"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},	{"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},	{"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},	{"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},	{"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},	{"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},	{"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},	{"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},	{"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},	{"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},	{"tx_restart_queue", IXGBE_STAT(restart_queue)},	{"rx_long_length_errors", IXGBE_STAT(stats.roc)},	{"rx_short_length_errors", IXGBE_STAT(stats.ruc)},	{"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},	{"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},	{"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},	{"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},	{"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},	{"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},	{"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},	{"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},	{"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},	{"rx_header_split", IXGBE_STAT(rx_hdr_split)},	{"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},	{"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},};#define IXGBE_QUEUE_STATS_LEN \		((((struct ixgbe_adapter *)netdev->priv)->num_tx_queues + \		 ((struct ixgbe_adapter *)netdev->priv)->num_rx_queues) * \		 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))#define IXGBE_GLOBAL_STATS_LEN \	sizeof(ixgbe_gstrings_stats) / sizeof(struct ixgbe_stats)#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_QUEUE_STATS_LEN)static int ixgbe_get_settings(struct net_device *netdev,			      struct ethtool_cmd *ecmd){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);	ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);	ecmd->port = PORT_FIBRE;	ecmd->transceiver = XCVR_EXTERNAL;	if (netif_carrier_ok(adapter->netdev)) {		ecmd->speed = SPEED_10000;		ecmd->duplex = DUPLEX_FULL;	} else {		ecmd->speed = -1;		ecmd->duplex = -1;	}	ecmd->autoneg = AUTONEG_DISABLE;	return 0;}static int ixgbe_set_settings(struct net_device *netdev,			      struct ethtool_cmd *ecmd){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	if (ecmd->autoneg == AUTONEG_ENABLE ||	    ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)		return -EINVAL;	if (netif_running(adapter->netdev)) {		ixgbe_down(adapter);		ixgbe_reset(adapter);		ixgbe_up(adapter);	} else {		ixgbe_reset(adapter);	}	return 0;}static void ixgbe_get_pauseparam(struct net_device *netdev,				 struct ethtool_pauseparam *pause){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	struct ixgbe_hw *hw = &adapter->hw;	pause->autoneg = AUTONEG_DISABLE;	if (hw->fc.type == ixgbe_fc_rx_pause) {		pause->rx_pause = 1;	} else if (hw->fc.type == ixgbe_fc_tx_pause) {		pause->tx_pause = 1;	} else if (hw->fc.type == ixgbe_fc_full) {		pause->rx_pause = 1;		pause->tx_pause = 1;	}}static int ixgbe_set_pauseparam(struct net_device *netdev,				struct ethtool_pauseparam *pause){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	struct ixgbe_hw *hw = &adapter->hw;	if (pause->autoneg == AUTONEG_ENABLE)		return -EINVAL;	if (pause->rx_pause && pause->tx_pause)		hw->fc.type = ixgbe_fc_full;	else if (pause->rx_pause && !pause->tx_pause)		hw->fc.type = ixgbe_fc_rx_pause;	else if (!pause->rx_pause && pause->tx_pause)		hw->fc.type = ixgbe_fc_tx_pause;	else if (!pause->rx_pause && !pause->tx_pause)		hw->fc.type = ixgbe_fc_none;	hw->fc.original_type = hw->fc.type;	if (netif_running(adapter->netdev)) {		ixgbe_down(adapter);		ixgbe_up(adapter);	} else {		ixgbe_reset(adapter);	}	return 0;}static u32 ixgbe_get_rx_csum(struct net_device *netdev){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);}static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	if (data)		adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;	else		adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;	if (netif_running(netdev)) {		ixgbe_down(adapter);		ixgbe_up(adapter);	} else {		ixgbe_reset(adapter);	}	return 0;}static u32 ixgbe_get_tx_csum(struct net_device *netdev){	return (netdev->features & NETIF_F_HW_CSUM) != 0;}static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data){	if (data)		netdev->features |= NETIF_F_HW_CSUM;	else		netdev->features &= ~NETIF_F_HW_CSUM;	return 0;}static int ixgbe_set_tso(struct net_device *netdev, u32 data){	if (data) {		netdev->features |= NETIF_F_TSO;		netdev->features |= NETIF_F_TSO6;	} else {		netdev->features &= ~NETIF_F_TSO;		netdev->features &= ~NETIF_F_TSO6;	}	return 0;}static u32 ixgbe_get_msglevel(struct net_device *netdev){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	return adapter->msg_enable;}static void ixgbe_set_msglevel(struct net_device *netdev, u32 data){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	adapter->msg_enable = data;}static int ixgbe_get_regs_len(struct net_device *netdev){#define IXGBE_REGS_LEN  1128	return IXGBE_REGS_LEN * sizeof(u32);}#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_static void ixgbe_get_regs(struct net_device *netdev,			   struct ethtool_regs *regs, void *p){	struct ixgbe_adapter *adapter = netdev_priv(netdev);	struct ixgbe_hw *hw = &adapter->hw;	u32 *regs_buff = p;	u8 i;	memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));	regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;	/* General Registers */	regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);	regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);	regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);	regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);	regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);	regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);	regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);	regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);	/* NVM Register */	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);	regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);	regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);	regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);	regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);	regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);	regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);	regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);	/* Interrupt */	regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICR);	regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);	regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);	regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);	regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);	regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);	regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));	regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));	regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);	regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);	regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL);	regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);	/* Flow Control */	regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);	regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));	regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));	regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));