哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌
AMI-BIOS CHECK-POINT, (C)1991 American Megatrends Inc.,All Rights Reserved
1346 Oakbrook Dr. #120. GA-30093. Phone:(404)-263-8181, Fax:(404)-263-9381
哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌哌
                  
POSTcodes for AMI HiFlex ISA/EISA BIOS (Date: 02/15/1991)

POSTcode     TEST-DESCRIPTION

  01         Processor register test about to start,
             and NMI to be disabled.

  02         NMI is DIsabled.
             Power on delay starting.

  03         Power on delay complete.
             Any initialization before keyboard BAT is in progress.

  04         Any initialization before keyboard BAT is complete.
             Reading keyboard SYS bit, to check soft reset/ power-on.

  05         Soft reset/ power-on determined.
             Going to enable ROM. i.e. disable shadow RAM/Cache if any.

  06         ROM is enabled. Calculating ROM BIOS checksum, and waiting
             for KB controller input buffer to be free.

  07         ROM BIOS checksum passed, KB controller I/B free.
             Going to issue the BAT command to keyboard controller.

  08         BAT command to keyboard controller is issued.
             Going to verify the BAT command.

  09         Keyboard controller BAT result verified.
             Keyboard command byte to be written next.

  0A         Keyboard command byte code is issued.
             Going to write command byte data.

  0B         Keyboard controller command byte is written.
             Going to issue Pin-23,24 blocking/unblocking command.

  0C         Pin-23,24 of keyboard controller is blocked/ unblocked.
             NOP command of keyboard controller to be issued next.

  0D         NOP command processing is done.
             CMOS shutdown register test to be done next.

  0E         CMOS shutdown register R/W test passed.
             Going to calculate CMOS checksum, and update DIAG byte.

  0F         CMOS checksum calculation is done, DIAG byte written.
             CMOS init. to begin (If "INIT CMOS IN EVERY BOOT IS SET").

  10         CMOS initialization done (if any).
             CMOS status register about to init for Date and Time.

  11         CMOS Status register initialised.
             Going to disable DMA and Interrupt controllers.

  12         DMA controller #1,#2, interrupt controller #1,#2 disabled.
             About to disable Video display and init port-B.

  13         Video display is disabled and port-B is initialized.
             Chipset init / auto memory detection about to begin.

  14         Chipset initialization / auto memory detection over.
             8254 timer test about to start.

  15         CH-2 timer test halfway.
             8254 CH-2 timer test to be complete.

  16         Ch-2 timer test over.
             8254 CH-1 timer test to be complete.

  17         CH-1 timer test over.
             8254 CH-0 timer test to be complete.

  18         CH-0 timer test over.
             About to start memory refresh.

  19         Memory Refresh started.
             Memory Refresh test to be done next.

  1A         Memory Refresh line is toggling.
             Going to check 15 micro second ON/OFF time.

  1B         Memory Refresh period 30 micro second test complete.
             Base 64K memory test about to start.

  20         Base 64k memory test started.
             Address line test to be done next.

  21         Address line test passed.
             Going to do toggle parity.

  22         Toggle parity over.
             Going for sequential data R/W test.

  23         Base 64k sequential data R/W test passed.
             Any setup before Interrupt vector init about to start.

  24         Setup required before vector initialzation complete.
             Interrupt vector initialization about to begin.

  25         Interrupt vector initialization done.
             Going to read I/O port of 8042 for turbo switch (if any).

  26         I/O port of 8042 is read.
             Going to initialize global data for turbo switch.

  27         Global data initialization is over.
             Any initialization after interrupt vector to be done next.

  28         Initialization after interrupt vector is complete.
             Going for monochrome mode setting.

  29         Monochrome mode setting is done.
             Going for Color mode setting.

  2A         Color mode setting is done.
             About to go for toggle parity before optional rom test.

  2B         Toggle parity over. About to give control for any
             setup required before optional video ROM check.

  2C         Processing before video ROM control is done.
             About to look for optional video ROM and give control.

  2D         Optional video ROM control is done. About to give control
             to do any procesing after video ROM returns control.

  2E         Return from processing after the video ROM control.
             If EGA/VGA not found then do display memory R/W test.

  2F         EGA/VGA not found.
             Display memory R/W test about to begin.

  30         Display memory R/W test passed.
             About to look for the retrace checking.

  31         Display memory R/W test or retrace checking failed.
             About to do alternate Display memory R/W test.

  32         Alternate Display memory R/W test passed.
             About to look for the alternate display retrace checking.

  33         Video display checking over. Verification of display
             type with switch setting and actual card to begin.

  34         Verification of display adapter done.
             Display mode to be set next.

  35         Display mode set complete.
             BIOS ROM data area about to be checked.

  36         BIOS ROM data area check over.
             Going to set cursor for power on message.

  37         Cursor setting for power on message id complete.
             Going to display the power on message.

  38         Power on message display complete.
             Going to read new cursor positon.

  39         New cursor position read and saved.
             Going to display the reference string.

  3A         Reference string display is over.
             Going to display the Hit <ESC> message.

  3B         Hit <ESC> message displayed.
             Virtual mode memory test about to start.

  40         Preperation for virtual mode test started.
             Going to verify from video memory.

  41         Returned after verifying from display memory.
             Going to prepare the descriptor tables.

  42         Descriptor tables prepared.
             Going to enter in virtual mode for memory test.

  43         Entered in the virtual mode.
             Going to enable interrupts for diagnostics mode.

  44         Interrupts enabled (if diagnostics switch is on).
             Going to initialize data to check memory wrap around at 0:0.

  45         Data initialized. Going to check for memory wrap around at 0:0
             and finding the total system memory size.

  46         Memory wrap around test done. Memory size calculation over.
             About to go for writing patterns to test memory.

  47         Pattern to be tested written in extended memory.
             Going to write patterns in base 640k memory.

  48         Patterns written in base memory.
             Going to findout amount of memory below 1M memory.

  49         Amount of memory below 1M found and verified.	
             Going to findout amount of memory above 1M memory.