?? uwb.mdl
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Model {
Name "uwb"
Version 5.1
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions on
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
SortedOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
PostLoadFcn "uwb_init;"
Created "Fri Nov 29 17:33:10 2002"
Creator "Martin Clark"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "mclark"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu Mar 04 14:39:15 2004"
ModelVersionFormat "1.%<AutoIncrement:937>"
ConfigurationManager "None"
SimParamPage "Diagnostics"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock off
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "FixedStepDiscrete"
SolverMode "SingleTasking"
StartTime "0.0"
StopTime "inf"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime off
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput off
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "none"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
RTWOptions "-aEnforceIntegerDowncast=1 -aExtMode=0 -aExtModeTes"
"ting=0 -aFoldNonRolledExpr=1 -aForceParamTrailComments=0 -aGenerateComments=1"
" -aGenerateReport=0 -aIgnoreCustomStorageClasses=0 -aIncDataTypeInIds=0 -aInc"
"HierarchyInIds=0 -aInlineInvariantSignals=0 -aInlinedPrmAccess=\"Literals\" -"
"aLocalBlockOutputs=1 -aLogVarNameModifier=\"rt_\" -aMaxRTWIdLen=31 -aPrefixMo"
"delToSubsysFcnNames=1 -aRTWVerbose=1 -aRollThreshold=5 -aShowEliminatedStatem"
"ents=0"
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Abs
SaturateOnIntegerOverflow on
ZeroCross on
}
Block {
BlockType ComplexToRealImag
Output "Real and imag"
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
DataType "auto"
SaturateOnIntegerOverflow on
}
Block {
BlockType DiscreteFilter
Numerator "[1]"
Denominator "[1 2]"
Realization "auto"
RTWStateStorageClass "Auto"
}
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType FrameConversion
OutFrame "Frame-based"
}
Block {
BlockType From
}
Block {
BlockType FromWorkspace
VariableName "simulink_input"
Interpolate on
OutputAfterFinalValue "Extrapolation"
}
Block {
BlockType Fcn
Expr "sin(u[1])"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ShowAdditionalParam off
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Goto
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
ShowAdditionalParam off
AllPortsSameDT on
OutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
}
Block {
BlockType MagnitudeAngleToComplex
Input "Magnitude and angle"
ConstantPart "0"
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
}
Block {
BlockType Merge
Inputs "2"
InitialOutput "[]"
AllowUnequalInputPortWidths off
InputPortOffsets "[]"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Probe
ProbeWidth on
ProbeSampleTime on
ProbeComplexSignal on
ProbeSignalDimensions off
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType RelationalOperator
Operator ">="
ShowAdditionalParam off
InputSameDT on
LogicOutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
ZeroCross on
}
Block {
BlockType Selector
InputType "Vector"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType UnitDelay
X0 "0"
RTWStateStorageClass "Auto"
}
Block {
BlockType ZeroOrderHold
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "uwb"
Location [12, 76, 720, 508]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator1"
Ports [0, 1]
Position [15, 123, 80, 167]
BackgroundColor "lightBlue"
DropShadow on
ShowName off
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
P "0.5"
seed "61"
Ts "uwb.bitPeriod"
frameBased on
sampPerFrame "uwb.bitsPerBlock"
orient off
}
Block {
BlockType Display
Name "Bit Rate1"
Ports [1]
Position [245, 187, 330, 253]
BackgroundColor "[1.000000, 1.000000, 0.658824]"
DropShadow on
ShowName off
Decimation "1"
}
Block {
BlockType SubSystem
Name "Convolutional Encoder"
Ports [1, 1]
Position [120, 127, 175, 163]
BackgroundColor "lightBlue"
DropShadow on
ShowName off
TreatAsAtomicUnit off
MaskDisplay "disp('Rate 5/8\\nEncoder')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Convolutional Encoder"
Location [58, 337, 666, 437]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [65, 38, 95, 52]
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