{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 26 14:03:31 2008 " "Info: Processing started: Mon May 26 14:03:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myjiaotongdeng -c myjiaotongdeng " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myjiaotongdeng -c myjiaotongdeng" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myjiaotongdeng.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file myjiaotongdeng.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 myjiaotongdeng " "Info: Found entity 1: myjiaotongdeng" {  } { { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiao_tong.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jiao_tong.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jiao_tong-one " "Info: Found design unit 1: jiao_tong-one" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jiao_tong " "Info: Found entity 1: jiao_tong" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "myjiaotongdeng " "Info: Elaborating entity \"myjiaotongdeng\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jiao_tong jiao_tong:inst1 " "Info: Elaborating entity \"jiao_tong\" for hierarchy \"jiao_tong:inst1\"" {  } { { "myjiaotongdeng.bdf" "inst1" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 120 480 600 312 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data jiao_tong.vhd(192) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(192): inferring latch(es) for signal or variable \"data\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "scan jiao_tong.vhd(192) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(192): inferring latch(es) for signal or variable \"scan\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[0\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"scan\[0\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[1\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"scan\[1\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[0\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"data\[0\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[1\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"data\[1\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[2\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"data\[2\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[3\] jiao_tong.vhd(192) " "Info (10041): Inferred latch for \"data\[3\]\" at jiao_tong.vhd(192)" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "jiao_tong:inst1\|g2 jiao_tong:inst1\|r2 " "Info: Duplicate register \"jiao_tong:inst1\|g2\" merged to single register \"jiao_tong:inst1\|r2\", power-up level changed" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|myjiaotongdeng\|jiao_tong:inst1\|stx 4 " "Info: State machine \"\|myjiaotongdeng\|jiao_tong:inst1\|stx\" contains 4 states" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|myjiaotongdeng\|jiao_tong:inst1\|stx " "Info: Selected Auto state machine encoding method for state machine \"\|myjiaotongdeng\|jiao_tong:inst1\|stx\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|myjiaotongdeng\|jiao_tong:inst1\|stx " "Info: Encoding result for state machine \"\|myjiaotongdeng\|jiao_tong:inst1\|stx\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst1\|stx.st4 " "Info: Encoded state bit \"jiao_tong:inst1\|stx.st4\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst1\|stx.st3 " "Info: Encoded state bit \"jiao_tong:inst1\|stx.st3\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst1\|stx.st2 " "Info: Encoded state bit \"jiao_tong:inst1\|stx.st2\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst1\|stx.st1 " "Info: Encoded state bit \"jiao_tong:inst1\|stx.st1\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myjiaotongdeng\|jiao_tong:inst1\|stx.st1 0000 " "Info: State \"\|myjiaotongdeng\|jiao_tong:inst1\|stx.st1\" uses code string \"0000\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myjiaotongdeng\|jiao_tong:inst1\|stx.st2 0011 " "Info: State \"\|myjiaotongdeng\|jiao_tong:inst1\|stx.st2\" uses code string \"0011\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myjiaotongdeng\|jiao_tong:inst1\|stx.st3 0101 " "Info: State \"\|myjiaotongdeng\|jiao_tong:inst1\|stx.st3\" uses code string \"0101\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myjiaotongdeng\|jiao_tong:inst1\|stx.st4 1001 " "Info: State \"\|myjiaotongdeng\|jiao_tong:inst1\|stx.st4\" uses code string \"1001\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jiao_tong:inst1\|counter\[0\] jiao_tong:inst1\|cnt\[0\] " "Info: Duplicate register \"jiao_tong:inst1\|counter\[0\]\" merged to single register \"jiao_tong:inst1\|cnt\[0\]\"" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 39 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "jiao_tong:inst1\|cnt\[1\] data_in GND " "Warning (14130): Reduced register \"jiao_tong:inst1\|cnt\[1\]\" with stuck data_in port to stuck value GND" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 185 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|scan\[1\] " "Warning: LATCH primitive \"jiao_tong:inst1\|scan\[1\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|scan\[0\] " "Warning: LATCH primitive \"jiao_tong:inst1\|scan\[0\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|data\[0\] " "Warning: LATCH primitive \"jiao_tong:inst1\|data\[0\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|data\[1\] " "Warning: LATCH primitive \"jiao_tong:inst1\|data\[1\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|data\[2\] " "Warning: LATCH primitive \"jiao_tong:inst1\|data\[2\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst1\|data\[3\] " "Warning: LATCH primitive \"jiao_tong:inst1\|data\[3\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 192 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Info: Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "100 " "Info: Implemented 100 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 26 14:03:34 2008 " "Info: Processing ended: Mon May 26 14:03:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}