{ "Info" "ITDB_TSU_RESULT" "jiao_tong:inst1\|qh\[1\] key1 clk -0.280 ns register " "Info: tsu for register \"jiao_tong:inst1\|qh\[1\]\" (data pin = \"key1\", clock pin = \"clk\") is -0.280 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.430 ns + Longest pin register " "Info: + Longest pin to register delay is 9.430 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key1 1 PIN PIN_97 20 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 20; PIN Node = 'key1'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 200 208 376 216 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.713 ns) + CELL(0.535 ns) 8.242 ns jiao_tong:inst1\|qh\[3\]~630 2 COMB LCCOMB_X24_Y9_N24 3 " "Info: 2: + IC(6.713 ns) + CELL(0.535 ns) = 8.242 ns; Loc. = LCCOMB_X24_Y9_N24; Fanout = 3; COMB Node = 'jiao_tong:inst1\|qh\[3\]~630'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.248 ns" { key1 jiao_tong:inst1|qh[3]~630 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.855 ns) 9.430 ns jiao_tong:inst1\|qh\[1\] 3 REG LCFF_X24_Y9_N7 5 " "Info: 3: + IC(0.333 ns) + CELL(0.855 ns) = 9.430 ns; Loc. = LCFF_X24_Y9_N7; Fanout = 5; REG Node = 'jiao_tong:inst1\|qh\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.188 ns" { jiao_tong:inst1|qh[3]~630 jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.384 ns ( 25.28 % ) " "Info: Total cell delay = 2.384 ns ( 25.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.046 ns ( 74.72 % ) " "Info: Total interconnect delay = 7.046 ns ( 74.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.430 ns" { key1 jiao_tong:inst1|qh[3]~630 jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.430 ns" { key1 {} key1~combout {} jiao_tong:inst1|qh[3]~630 {} jiao_tong:inst1|qh[1] {} } { 0.000ns 0.000ns 6.713ns 0.333ns } { 0.000ns 0.994ns 0.535ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.670 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.011 ns) + CELL(0.970 ns) 4.121 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X21_Y12_N17 3 " "Info: 2: + IC(2.011 ns) + CELL(0.970 ns) = 4.121 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.970 ns) 6.204 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X21_Y9_N15 9 " "Info: 3: + IC(1.113 ns) + CELL(0.970 ns) = 6.204 ns; Loc. = LCFF_X21_Y9_N15; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.083 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.948 ns) + CELL(0.000 ns) 8.152 ns jiao_tong:inst1\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 16 " "Info: 4: + IC(1.948 ns) + CELL(0.000 ns) = 8.152 ns; Loc. = CLKCTRL_G6; Fanout = 16; COMB Node = 'jiao_tong:inst1\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.948 ns" { jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 9.670 ns jiao_tong:inst1\|qh\[1\] 5 REG LCFF_X24_Y9_N7 5 " "Info: 5: + IC(0.852 ns) + CELL(0.666 ns) = 9.670 ns; Loc. = LCFF_X24_Y9_N7; Fanout = 5; REG Node = 'jiao_tong:inst1\|qh\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 38.74 % ) " "Info: Total cell delay = 3.746 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.924 ns ( 61.26 % ) " "Info: Total interconnect delay = 5.924 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|qh[1] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.430 ns" { key1 jiao_tong:inst1|qh[3]~630 jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.430 ns" { key1 {} key1~combout {} jiao_tong:inst1|qh[3]~630 {} jiao_tong:inst1|qh[1] {} } { 0.000ns 0.000ns 6.713ns 0.333ns } { 0.000ns 0.994ns 0.535ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|qh[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|qh[1] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[6\] jiao_tong:inst1\|q1\[3\] 19.364 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[6\]\" through register \"jiao_tong:inst1\|q1\[3\]\" is 19.364 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.011 ns) + CELL(0.970 ns) 4.121 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X21_Y12_N17 3 " "Info: 2: + IC(2.011 ns) + CELL(0.970 ns) = 4.121 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.970 ns) 6.204 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X21_Y9_N15 9 " "Info: 3: + IC(1.113 ns) + CELL(0.970 ns) = 6.204 ns; Loc. = LCFF_X21_Y9_N15; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.083 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.948 ns) + CELL(0.000 ns) 8.152 ns jiao_tong:inst1\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 16 " "Info: 4: + IC(1.948 ns) + CELL(0.000 ns) = 8.152 ns; Loc. = CLKCTRL_G6; Fanout = 16; COMB Node = 'jiao_tong:inst1\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.948 ns" { jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 9.670 ns jiao_tong:inst1\|q1\[3\] 5 REG LCFF_X24_Y9_N29 4 " "Info: 5: + IC(0.852 ns) + CELL(0.666 ns) = 9.670 ns; Loc. = LCFF_X24_Y9_N29; Fanout = 4; REG Node = 'jiao_tong:inst1\|q1\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[3] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 38.74 % ) " "Info: Total cell delay = 3.746 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.924 ns ( 61.26 % ) " "Info: Total interconnect delay = 5.924 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[3] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.390 ns + Longest register pin " "Info: + Longest register to pin delay is 9.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst1\|q1\[3\] 1 REG LCFF_X24_Y9_N29 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y9_N29; Fanout = 4; REG Node = 'jiao_tong:inst1\|q1\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst1|q1[3] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.149 ns) + CELL(0.624 ns) 1.773 ns jiao_tong:inst1\|Mux0~15 2 COMB LCCOMB_X24_Y8_N0 7 " "Info: 2: + IC(1.149 ns) + CELL(0.624 ns) = 1.773 ns; Loc. = LCCOMB_X24_Y8_N0; Fanout = 7; COMB Node = 'jiao_tong:inst1\|Mux0~15'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.773 ns" { jiao_tong:inst1|q1[3] jiao_tong:inst1|Mux0~15 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 194 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.616 ns) 3.555 ns jiao_tong:inst1\|Mux7~23 3 COMB LCCOMB_X21_Y9_N0 1 " "Info: 3: + IC(1.166 ns) + CELL(0.616 ns) = 3.555 ns; Loc. = LCCOMB_X21_Y9_N0; Fanout = 1; COMB Node = 'jiao_tong:inst1\|Mux7~23'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.782 ns" { jiao_tong:inst1|Mux0~15 jiao_tong:inst1|Mux7~23 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.202 ns) 4.120 ns jiao_tong:inst1\|seg7\[6\]~279 4 COMB LCCOMB_X21_Y9_N20 1 " "Info: 4: + IC(0.363 ns) + CELL(0.202 ns) = 4.120 ns; Loc. = LCCOMB_X21_Y9_N20; Fanout = 1; COMB Node = 'jiao_tong:inst1\|seg7\[6\]~279'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { jiao_tong:inst1|Mux7~23 jiao_tong:inst1|seg7[6]~279 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.164 ns) + CELL(3.106 ns) 9.390 ns 78leddata\[6\] 5 PIN PIN_115 0 " "Info: 5: + IC(2.164 ns) + CELL(3.106 ns) = 9.390 ns; Loc. = PIN_115; Fanout = 0; PIN Node = '78leddata\[6\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.270 ns" { jiao_tong:inst1|seg7[6]~279 78leddata[6] } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 160 656 832 176 "78leddata\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.548 ns ( 48.43 % ) " "Info: Total cell delay = 4.548 ns ( 48.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.842 ns ( 51.57 % ) " "Info: Total interconnect delay = 4.842 ns ( 51.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.390 ns" { jiao_tong:inst1|q1[3] jiao_tong:inst1|Mux0~15 jiao_tong:inst1|Mux7~23 jiao_tong:inst1|seg7[6]~279 78leddata[6] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.390 ns" { jiao_tong:inst1|q1[3] {} jiao_tong:inst1|Mux0~15 {} jiao_tong:inst1|Mux7~23 {} jiao_tong:inst1|seg7[6]~279 {} 78leddata[6] {} } { 0.000ns 1.149ns 1.166ns 0.363ns 2.164ns } { 0.000ns 0.624ns 0.616ns 0.202ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[3] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.390 ns" { jiao_tong:inst1|q1[3] jiao_tong:inst1|Mux0~15 jiao_tong:inst1|Mux7~23 jiao_tong:inst1|seg7[6]~279 78leddata[6] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.390 ns" { jiao_tong:inst1|q1[3] {} jiao_tong:inst1|Mux0~15 {} jiao_tong:inst1|Mux7~23 {} jiao_tong:inst1|seg7[6]~279 {} 78leddata[6] {} } { 0.000ns 1.149ns 1.166ns 0.363ns 2.164ns } { 0.000ns 0.624ns 0.616ns 0.202ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key1 led3 14.705 ns Longest " "Info: Longest tpd from source pin \"key1\" to destination pin \"led3\" is 14.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key1 1 PIN PIN_97 20 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 20; PIN Node = 'key1'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 200 208 376 216 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.734 ns) + CELL(0.651 ns) 8.379 ns jiao_tong:inst1\|rb~4 2 COMB LCCOMB_X22_Y9_N30 2 " "Info: 2: + IC(6.734 ns) + CELL(0.651 ns) = 8.379 ns; Loc. = LCCOMB_X22_Y9_N30; Fanout = 2; COMB Node = 'jiao_tong:inst1\|rb~4'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.385 ns" { key1 jiao_tong:inst1|rb~4 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.190 ns) + CELL(3.136 ns) 14.705 ns led3 3 PIN PIN_4 0 " "Info: 3: + IC(3.190 ns) + CELL(3.136 ns) = 14.705 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'led3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.326 ns" { jiao_tong:inst1|rb~4 led3 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 256 656 832 272 "led3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.781 ns ( 32.51 % ) " "Info: Total cell delay = 4.781 ns ( 32.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.924 ns ( 67.49 % ) " "Info: Total interconnect delay = 9.924 ns ( 67.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.705 ns" { key1 jiao_tong:inst1|rb~4 led3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "14.705 ns" { key1 {} key1~combout {} jiao_tong:inst1|rb~4 {} led3 {} } { 0.000ns 0.000ns 6.734ns 3.190ns } { 0.000ns 0.994ns 0.651ns 3.136ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}