module ctrl_eth (
	wb_clk_i,wb_rst_i,
	wb_adr_o,wb_dat_i,wb_dat_o,
	wb_sel_o,wb_we_o, wb_stb_o,wb_cyc_o,
	wb_ack_i,led
);		
input        wb_clk_i;
input        wb_rst_i;
input        wb_ack_i;    
input[31:0]  wb_dat_i;  
output[31:0] wb_adr_o;
output[31:0] wb_dat_o;
output[3:0]  wb_sel_o;
output       wb_we_o;  
output       wb_stb_o;  
output       wb_cyc_o;  

output  led;
reg  led;

reg[31:0]   wb_adr_o;
reg[31:0]   wb_dat_o;
reg[3:0]    wb_sel_o;
reg         wb_we_o;  
reg         wb_stb_o;  
reg         wb_cyc_o;  


reg[8 : 0]  State;
parameter   sta0 = 9'b0_0000_0001;
parameter   sta1 = 9'b0_0000_0010;
parameter   sta2 = 9'b0_0000_0100;
parameter   sta3 = 9'b0_0000_1000;
parameter   sta4 = 9'b0_0001_0000;
parameter   sta5 = 9'b0_0010_0000;
parameter   sta6 = 9'b0_0100_0000;
parameter   sta7 = 9'b0_1000_0000;
parameter   sta8 = 9'b1_0000_0000;


 parameter init_dat0   = 65'h1_9200000b_00000010;
 parameter init_dat1   = 65'h1_92000002_00000001;
 parameter init_dat2   = 65'h1_92000003_00000001;
 parameter init_dat3   = 65'h0_92000004_00000000;
 
 parameter init_dat4   = 65'h1_92000007_00000000;
 parameter init_dat5   = 65'h1_92000008_00000000;
 parameter init_dat6   = 65'h1_92000009_00000000;
 parameter init_dat7   = 65'h1_9200000a_00000000;

 parameter init_dat8   = 65'h1_92000002_00000002;
 parameter init_dat9   = 65'h1_92000003_00000001;
 parameter init_dat10  = 65'h0_92000004_00000000;  
 parameter init_dat11  = 65'h0_92000010_00000000;

reg[64 : 0] rom_dat;
reg[64 : 0] ram_dat;

reg[64 : 0] send_dat;

reg[31 : 0] rw_dat;
reg[8 : 0]  cnt;
reg[7:0]    temp;
reg[6:0]    addr;

reg         init_sel;
reg         rw_ctrl; 
reg         rom_or_ram;

always @(posedge wb_clk_i or posedge wb_rst_i)
begin
 if(wb_rst_i)
 begin
  wb_cyc_o  <= 1'b0;
  wb_stb_o  <= 1'b0; 
 end
 else if(init_sel)
 begin  
   wb_adr_o <= send_dat[63:32];
   wb_dat_o <= send_dat[31: 0]; 
   rw_ctrl  <= send_dat[64]; 
   wb_sel_o <= 4'b1111;
   wb_cyc_o <= 1'b1;
   wb_stb_o <= 1'b1; 
   if(send_dat[64]) wb_we_o  <= 1'b1; 
   else             wb_we_o  <= 1'b0;       
 end
 else if(wb_ack_i)
 begin
  wb_cyc_o <= 1'b0;
  wb_stb_o <= 1'b0;  
  if(rw_ctrl)  rw_dat <= 32'd0;
  else         rw_dat <= wb_dat_i;
 end 
end

always @( * )
begin
 if(rom_or_ram)
  send_dat = rom_dat;
 else
  send_dat = ram_dat;
end

always @(addr[4:0])
begin
  rom_dat = 65'h0_00000000_00000000;
 case(addr[4:0])
  5'd0   : rom_dat =  init_dat0;
  5'd1   : rom_dat =  init_dat1;	
  5'd2   : rom_dat =  init_dat2;	
  5'd3   : rom_dat =  init_dat3;
  5'd4   : rom_dat =  init_dat4;
  5'd5   : rom_dat =  init_dat5;
  5'd6   : rom_dat =  init_dat6;
  5'd7   : rom_dat =  init_dat7;
  
  5'd8   : rom_dat =  init_dat8;
  5'd9   : rom_dat =  init_dat9;	
  5'd10  : rom_dat =  init_dat10;	
  5'd11  : rom_dat =  init_dat11;
  5'd12  : rom_dat =  init_dat0;
  5'd13  : rom_dat =  init_dat0;
  5'd14  : rom_dat =  init_dat0;
  5'd15  : rom_dat =  init_dat0;
  default: rom_dat =  init_dat0;
 endcase
end

wire rst_ni;
reg  rst_dly1;
reg  rst_dly2;

assign rst_ni = rst_dly1 & ( ~rst_dly2);
always@(posedge wb_clk_i)
begin
 rst_dly1  <= wb_rst_i;
 rst_dly2  <= rst_dly1;
end
 
always @(posedge wb_clk_i or posedge rst_ni)
begin
  if(rst_ni) 
    begin
       led <= 1'b0;
       init_sel   <= 1'b0;
       cnt        <= 8'd0;
       addr       <= 7'd0; 
       temp       <= 8'd0;  

       rom_or_ram <= 1'b1;
       ram_dat    <= 65'd0; 
       State      <= sta0;   
    end 
  else  
  case(State)
	sta0:
	   begin
       init_sel  <=1'b0;
       cnt       <=9'd0;
       addr      <=7'd0; 
       temp      <=8'd0;  
       State     <=sta1;  
   	   end
	sta1:
	   begin
   	    if(temp == 8'd1)  init_sel   <= 1'b1;
	    if(temp == 8'd2)  init_sel   <= 1'b0;
	    if(wb_ack_i)
	    begin 
           temp   <= 8'd0;
	       State  <= sta2;
	    end
	    else temp <= temp + 1'b1;
	   end
	sta2:
	   begin
	    if(cnt == 9'd3 )
	     begin
	        State <= sta3;
	     end
	    else  
	      begin
   	        cnt    <= cnt + 1'b1;
            addr   <= addr + 1'b1; 
   	        State  <= sta1; 
   	      end        
   	   end
   	sta3:
	   begin
	     if(rw_dat[7:0] == 8'h01)
	      begin 
	        State   <= sta1; 
	      end
	     else
	      begin 
  	        cnt        <= 9'd4;
	        addr       <= 8'd4; 
         	temp       <= 8'd0;
	        State      <= sta4;  
	      end 
   	   end
       

	sta4:
	   begin
   	    if(temp == 8'd1)  init_sel   <= 1'b1;
	    if(temp == 8'd2)  init_sel   <= 1'b0;
	    if(wb_ack_i)
	    begin 
           temp   <= 8'd0;
	       State  <= sta5;
	    end
	    else temp <= temp + 1'b1;
	   end
	sta5:
	   begin
	    if(cnt == 9'd10 )
	     begin
	        State <= sta6;
	     end
	    else  
	      begin
   	        cnt    <= cnt + 1'b1;
            addr   <= addr + 1'b1; 
   	        State  <= sta4; 
   	      end        
   	   end
   	sta6:
	   begin
	     if(rw_dat[7:0] == 8'h01)
	      begin 
	        State   <= sta4; 
	      end
	     else
	      begin 
  	        cnt        <= 9'd0;
	        addr       <= 8'd11; 
         	temp       <= 8'd0;
	        State      <= sta7;  
	      end 
   	   end
       
    sta7:
	   begin
   	    if(temp == 8'd1)  init_sel   <= 1'b1;
	    if(temp == 8'd2)  init_sel   <= 1'b0;
	    if(wb_ack_i)
	    begin 
           temp   <= 8'd0;
	       State  <= sta8;
	    end
	    else 
	     begin
	      temp <= temp + 1'b1;
	     end 
	   end
    sta8:
	   begin
	     led <= 1'b1;
	     if( cnt == 9'd511 )
           State  <= sta8;   
         else
          begin
	       cnt    <= cnt + 1'b1;
	       State  <= sta7;  
	      end  
	   end


	default :
	begin
		State <= sta0;
	end
  endcase
end

endmodule