LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;						//調用庫
ENTITY  ENCODER IS								//實體部分，描述電路功能
  PORT (i:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         y:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENCODER; 
ARCHITECTURE six OF ENCODER IS					
BEGIN 
PROCESS(i) 										//進程開始
BEGIN 
IF  i(7)='1' THEN y<="111";						//如果輸入為1，則輸出值
ELSIF i(6)='1' THEN y <="110";
ELSIF i(5)='1' THEN y <="101";
ELSIF i(4)='1' THEN y <="100";
ELSIF i(3)='1' THEN y <="011";
ELSIF i(2)='1' THEN y <="010";
ELSIF i(1)='1' THEN y <="001";
ELSIF i(0)='1' THEN y <="000";
ELSE y <="XXX";
END IF ;
END PROCESS;									//結束進程
END six;