?? 模64計數(shù)器.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY updncount64 IS
PORT(Clk,clr,UPDOWN:IN STD_LOGIC;
qa,qb,qc,qd,qe,qf:OUT STD_LOGIC);//輸出6位二進制數(shù)最大為63,所以是64進制計數(shù)器
End updncount64;
ARCHITECTURE ART OF updncount64 IS //圖5-4 加減計數(shù)器仿波形
Signal count_6:STD_LOGIC_VECTOR(5 DOWNTO 0);
Begin
qa= count_6(0);
qb= count_6(1);
qc= count_6(2);
qd= count_6(3);
qe= count_6(4);
qf= count_6(5);
process(clk,clr)
BEGIN
IF(clr='0')THEN
Count_6=000000;
ELSIF(CLK'EVENT AND CLK='1')THEN -
IF(updn='1')THEN
Count_6= Count_6+1;
ELSE
Count_6= Count_6-1; //為減1 計數(shù)器
END IF;
END IF;
END PROCESS;
END ART;
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -