LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;						//使用庫(kù)
ENTITY DEMUX4_1 IS								//實(shí)體部分，描述電路
PORT(a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);			//定義端口
     din: IN STD_LOGIC;
y0,y1,y2,y3:OUT STD_LOGIC);
END DEMUX4_1;									//結(jié)束實(shí)體部分
ARCHITECTURE nine OF DEMUX4_1 IS
BEGIN
PROCESS(a, y0,y1,y2,y3) 							//進(jìn)程開始
BEGIN
     y0<='0';y1<='0';y2<='0';y3<='0';					
	CASE a IS									//CASE語(yǔ)句
		WHEN "00"=>y0<=din;
		WHEN "01"=>y1<= din;
		WHEN "10"=>y2<= din;
		WHEN "11"=>y3<= din;
	     WHEN others=>y<='0';
	END CASE;
	END IF;
END PROCESS;
END nine ;