# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Full Version
# Date created = 09:45:27  July 10, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		train_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C70F896C6
set_global_assignment -name TOP_LEVEL_ENTITY train
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:45:27  JULY 10, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name VHDL_FILE debounce.vhd
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VERILOG_FILE train.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_location_assignment PIN_U30 -to clock
set_location_assignment PIN_T28 -to reset
set_location_assignment PIN_W25 -to switch1
set_location_assignment PIN_W23 -to switch2
set_location_assignment PIN_Y27 -to switch3
set_location_assignment PIN_Y24 -to dirA[0]
set_location_assignment PIN_Y23 -to dirA[1]
set_location_assignment PIN_AA27 -to dirB[0]
set_location_assignment PIN_AA24 -to dirB[1]
set_location_assignment PIN_AA23 -to sensor1
set_location_assignment PIN_AB26 -to sensor2
set_location_assignment PIN_AB25 -to sensor3
set_location_assignment PIN_AC27 -to sensor4
set_location_assignment PIN_AC26 -to sensor5
set_location_assignment PIN_AD15 -to CLOCK_50
set_global_assignment -name MISC_FILE "E:/exercises/train_4/train.dpf"
set_global_assignment -name VERILOG_FILE Verilog2.v
set_global_assignment -name VECTOR_WAVEFORM_FILE train.vwf