?? example 2-20.asm
字號:
;Example 2 - 20. Creation of a Sine Modulated PWM Signal ASM Listing Based on TLU Using TMS320F240
;*******************************************************************
; File Name: pwm1.asm
; Originator: Digital Control systems Apps group - Houston
; Target System: 'C240 Evaluation Board
;
; Description: Pulse Width Modulator - Sets up the registers
; for an asymmetric PWM output. The output is a
; square wave with a sine wave modulated duty cycle.
; PWM Period is 0.05ms => 20kHz
;
; Entering the command
; wa *FREQSTEP,,u
; Allows one to change the step size to change
; the frequency in the debugger environment
;
; Last Updated: 20 June 1997
;
;*******************************************************************
.include f240regs.h
;-------------------------------------------------------------------
; Vector address declarations
;-------------------------------------------------------------------
.sect ".vectors"
RSVECT B START ; Reset Vector
INT1 B PHANTOM ; Interrupt Level 1
INT2 B SINE ; Interrupt Level 2
INT3 B PHANTOM ; Interrupt Level 3
INT4 B PHANTOM ; Interrupt Level 4
INT5 B PHANTOM ; Interrupt Level 5
INT6 B PHANTOM ; Interrupt Level 6
RESERVED B PHANTOM ; Reserved
SW_INT8 B PHANTOM ; User S/W Interrupt
SW_INT9 B PHANTOM ; User S/W Interrupt
SW_INT10 B PHANTOM ; User S/W Interrupt
SW_INT11 B PHANTOM ; User S/W Interrupt
SW_INT12 B PHANTOM ; User S/W Interrupt
SW_INT13 B PHANTOM ; User S/W Interrupt
SW_INT14 B PHANTOM ; User S/W Interrupt
SW_INT15 B PHANTOM ; User S/W Interrupt
SW_INT16 B PHANTOM ; User S/W Interrupt
TRAP B PHANTOM ; Trap vector
NMINT B PHANTOM ; Non-maskable Interrupt
EMU_TRAP B PHANTOM ; Emulator Trap
SW_INT20 B PHANTOM ; User S/W Interrupt
SW_INT21 B PHANTOM ; User S/W Interrupt
SW_INT22 B PHANTOM ; User S/W Interrupt
SW_INT23 B PHANTOM ; User S/W Interrupt
;===================================================================
; MAIN CODE - starts here
;===================================================================
.text
NOP
START:
SETC INTM ;Disable interrupts
SPLK #0002h,IMR ;Mask all core interrupts
;except INT2
LACC IFR ;Read Interrupt flags
SACL IFR ;Clear all interrupt flags
CLRC SXM ;Clear Sign Extension Mode
CLRC OVM ;Reset Overflow Mode
CLRC CNF ;Config Block B0 to Data mem
;-----------------------------------
; Set up PLL Module
;-----------------------------------
LDP #00E0h
;The following line is necessary if a previous program set the PLL
;to a different ;setting than the settings which the application
;uses. By disabling the PLL, the CKCR1 register can be modified so
;that the PLL can run at the new settings when it is re-enabled.
SPLK #0000000001000001b,CKCR0 ;CLKMD=PLL Disable
;SYSCLK=CPUCLK/2
; 5432109876543210
SPLK #0000000010111011b,CKCR1
;CLKIN(OSC)=10MHz,CPUCLK=20MHz
; CKCR1 - Clock Control Register 1
; Bits 7-4 (1011) CKINF(3)-CKINF(0) - Crystal or Clock-In
; Frequency
; Frequency = 10MHz
; Bit 3 (1) PLLDIV(2) - PLL divide by 2 bit
; Divide PLL input by 2
; Bits 2-0 (011) PLLFB(2)-PLLFB(0) - PLL multiplication ratio
; PLL Multiplication Ration = 4
; 5432109876543210
SPLK #0000000011000001b,CKCR0 ;CLKMD=PLL Enable
;SYSCLK=CPUCLK/2
;CKCR0 - Clock Control Register 0
; Bits 7-6 (11) CLKMD(1),CLKMD(0) - Operational mode of
; Clock Module
; PLL Enabled; Run on CLKIN on exiting low
; power mode
; Bits 5-4 (00) PLLOCK(1),PLLOCK(0) - PLL Status.
; READ ONLY
; Bits 3-2 (00) PLLPM(1),PLLPM(0) - Low Power Mode
; LPM0
; Bit 1 (0) ACLKENA - 1MHz ACLK Enable
; ACLK Disabled
; Bit 0 (1) PLLPS - System Clock Prescale Value
; f(sysclk)=f(cpuclk)/2
; 5432109876543210
SPLK #0100000011000000b,SYSCR ;CLKOUT=CPUCLK
;SYSCR - System Control Register
; Bit 15-14 (01) RESET1,RESET0 - Software Reset Bits
; No Action
; Bits 13-8 (000000) Reserved
; Bit 7-6 (11) CLKSRC1,CLKSRC0 - CLKOUT-Pin Source
; Select
; CPUCLK: CPU clock output mode
; Bit 5-0 (000000)Reserved
SPLK #006Fh, WDCR ;Disable WD if VCCP=5V
;(JP5 in pos. 2-3)
KICK_DOG ;Reset Watchdog
;-----------------------------------
; Set up Digital I/O Port
;-----------------------------------
LDP #225 ;DP=225, Data Page to Configure OCRA
; 5432109876543210
SPLK #0011100000000000b,OCRA
;OCRA - Output Control Register A
; Bit 15 (0) CRA.15 - IOPB7
; Bit 14 (0) CRA.14 - IOPB6
; Bit 13 (1) CRA.13 - T3PWM/T3CMP
; Bit 12 (1) CRA.12 - T2PWM/T2CMP
; Bit 11 (1) CRA.11 - T1PWM/T1CMP
; Bit 10 (0) CRA.10 - IOPB2
; Bit 9 (0) CRA.9 - IOPB1
; Bit 8 (0) CRA.8 - IOPB0
; Bits 7-4 (0000) Reserved
; Bit 3 (0) CRA.3 - IOPA3
; Bit 2 (0) CRA.2 - IOPA2
; Bit 1 (0) CRA.1 - IOPA1
; Bit 0 (0) CRA.0 - IOPA0
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
;- Event Manager Module Reset
;*
SPRA411
16 Creating a Sine Modulated PWM Signal Using the TMS320F240 EVM
;- This section resets all of the Event Manager Module Registers.
;* This is necessary for silicon revision 1.1; however, for
;- silicon revisions 2.0 and later, this is not necessary
;*
;-
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
LDP #232 ;DP=232 Data Page for the Event Manager
SPLK #0000h,GPTCON ;Clear General Purpose Timer Control
SPLK #0000h,T1CON ;Clear GP Timer 1 Control
SPLK #0000h,T2CON ;Clear GP Timer 2 Control
SPLK #0000h,T3CON ;Clear GP Timer 3 Control
SPLK #0000h,COMCON ;Clear Compare Control
SPLK #0000h,ACTR
;Clear Full Compare Action Control Register
SPLK #0000h,SACTR
;Clear Simple Compare Action Control Register
SPLK #0000h,DBTCON
;Clear Dead-Band Timer Control Register
SPLK #0000h,CAPCON ;Clear Capture Control
SPLK #0FFFFh,EVIFRA ;Clear Interrupt Flag Register A
SPLK #0FFFFh,EVIFRB ;Clear Interrupt Flag Register B
SPLK #0FFFFh,EVIFRC ;Clear Interrupt Flag Register C
SPLK #0000h,EVIMRA ;Clear Event Manager Mask Register A
SPLK #0000h,EVIMRB ;Clear Event Manager Mask Register B
SPLK #0000h,EVIMRC ;Clear Event Manager Mask Register C
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
;- End of RESET section for silicon revision 1.1 *
;*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
;-----------------------------------
; Set up Event Manager Module
;-----------------------------------
T1COMPARE .set 0 ; T1Compare Initialized to 0
T1PERIOD .set 1000 ; T1Period Initialized to
;1000 = 20kHz value
.text
LDP #232 ;DP=232, Data Page for
;Event Manager Addresses
SPLK #T1COMPARE,T1CMPR;T1CMPR = 0
; 2109876543210
SPLK #0000001010101b,GPTCON
;GPTCON - GP Timer Control Register
; Bit 15 (0) T3STAT - GP Timer 3 Status. READ ONLY
; Bit 14 (0) T2STAT - GP Timer 2 Status. READ ONLY
; Bit 13 (0) T1STAT - GP Timer 1 Status. READ ONLY
; Bits 12-11 (00) T3TOADC - ADC start by event of GP Timer 3
; No event starts ADC
; Bits 10-9 (00) T2TOADC - ADC start by event of GP Timer 2
; No event starts ADC
; Bits 8-7 (00) T1TOADC - ADC start by event of GP Timer 1
; No event starts ADC
; Bit 6 (1) TCOMPOE - Compare output enable
; Enable all three GP timer compare outputs
; Bits 5-4 (01) T3PIN - Polarity of GP Timer 3 compare
; output
; Active Low
; Bits 3-2 (01) T2PIN - Polarity of GP Timer 2 compare
; output
; Active Low
; Bits 1-0 (01) T1PIN - Polarity of GP Timer 1 compare
; output
; Active Low
SPLK #T1PERIOD,T1PR ; T1PR = 1000
SPLK #0000h,T1CNT ; Initialize Timer 1
SPLK #0000h,T2CNT ; Initialize Timer 2
SPLK #0000h,T3CNT ; Initialize Timer 3
; 5432109876543210
SPLK #0001000000000110b,T1CON
;T1CON - GP Timer 1 Control Register
; Bits 15-14 (00) FREE,SOFT - Emulation Control Bits
; Stop immediately on emulation suspend
; Bits 13-11 (010) TMODE2-TMODE0 - Count Mode Selection
; Continuous-Up Count Mode
; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler
; Divide by 1
; Bit 7 (0) Reserved
; Bit 6 (0) TENABLE - Timer Enable
; Disable timer operations
; Bits 5-4 (00) TCLKS1,TCLKS0 - Clock Source Select
; Internal Clock Source
; Bits 3-2 (01) TCLD1,TCLD0 - Timer Compare Register
; Reload Condition
; When counter is 0 or equals period
; register value
; Bit 1 (1) TECMPR - Timer compare enable
; Enable timer compare operation
; Bit 0 (0) Reserved
; 5432109876543210
SPLK #0000000000000000b,T2CON ;Not used
;T2CON - GP Timer 2 Control Register
; Bits 15-14 (00) FREE,SOFT - Emulation Control Bits
; Stop immediately on emulation suspend
; Bits 13-11 (000) TMODE2-TMODE0 - Count Mode Selection
; Stop/Hold
; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler
; Divide by 1
; Bit 7 (0) TSWT1 - GP Timer 1 timer enable bit
; Use own TENABLE bit
; Bit 6 (0) TENABLE - Timer Enable
; Disable timer operations
; Bits 5-4 (00) TCLKS1,TCLKS0 - Clock Source Select
; Internal Clock Source
; Bits 3-2 (00) TCLD1,TCLD0 - Timer Compare Register
; Reload Condition When counter is 0
; Bit 1 (0) TECMPR - Timer compare enable
; Disable timer compare operation
; Bit 0 (0) SELT1PR - Period Register select
; Use own period register
; 5432109876543210
SPLK #0000000000000000b,T3CON ;Not Used
;T3CON - GP Timer 3 Control Register
; Bits 15-14 (00) FREE,SOFT - Emulation Control Bits
; Stop immediately on emulation suspend
; Bits 13-11 (000) TMODE2-TMODE0 - Count Mode Selection
; Stop/Hold
; Bits 10-8 (000) TPS2-TPS0 - Input Clock Prescaler
; Divide by 1
; Bit 7 (0) TSWT1 - GP Timer 1 timer enable bit
; Use own TENABLE bit
; Bit 6 (0) TENABLE - Timer Enable
; Disable timer operations
; Bits 5-4 (00) TCLKS1,TCLKS0 - Clock Source Select
; Internal Clock Source
; Bits 3-2 (00) TCLD1,TCLD0 - Timer Compare Register
; Reload Condition When counter is 0
; Bit 1 (0) TECMPR - Timer compare enable
; Disable timer compare operation
; Bit 0 (0) SELT1PR - Period Register select
; Use own period register
SBIT1 T1CON,B6_MSK ;Sets Bit 6 of T1CON
;T1CON - GP Timer 1 Control Register
; Bit 6 (1) TENABLE - Timer Enable
; Enable Timer Operations
SPLK #0FFFFh,EVIFRA ;Clear all pending interrupts
SPLK #0080h,EVIMRA ;Enable Timer 1 Period Interrupt
;-----------------------------------
; Generate Sine Wave Modulated PWM
;-----------------------------------
.bss TABLE,1 ;Keeps address of the pointer in
;the SINE Table
.bss TOPTABLE,1 ;Keeps the reset value for the
;pointer
.bss COMPARET1,1 ;A register to do calculations
;since the
;T1CMPR register is double
;buffered
.bss FREQSTEP,1 ;Frequency modulation of the sine
;wave
.bss MODREG,1 ;Rolling Modulo Register
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