/* * NetChip 2280 high/full speed USB device controller. * Unlike many such controllers, this one talks PCI. *//* * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) * Copyright (C) 2003 David Brownell * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA *//*-------------------------------------------------------------------------*//* NET2280 MEMORY MAPPED REGISTERS * * The register layout came from the chip documentation, and the bit * number definitions were extracted from chip specification. * * Use the shift operator ('<<') to build bit masks, with readl/writel * to access the registers through PCI. *//* main registers, BAR0 + 0x0000 */struct net2280_regs {	// offset 0x0000	u32		devinit;#define     LOCAL_CLOCK_FREQUENCY                               8#define     FORCE_PCI_RESET                                     7#define     PCI_ID                                              6#define     PCI_ENABLE                                          5#define     FIFO_SOFT_RESET                                     4#define     CFG_SOFT_RESET                                      3#define     PCI_SOFT_RESET                                      2#define     USB_SOFT_RESET                                      1#define     M8051_RESET                                         0	u32		eectl;#define     EEPROM_ADDRESS_WIDTH                                23#define     EEPROM_CHIP_SELECT_ACTIVE                           22#define     EEPROM_PRESENT                                      21#define     EEPROM_VALID                                        20#define     EEPROM_BUSY                                         19#define     EEPROM_CHIP_SELECT_ENABLE                           18#define     EEPROM_BYTE_READ_START                              17#define     EEPROM_BYTE_WRITE_START                             16#define     EEPROM_READ_DATA                                    8#define     EEPROM_WRITE_DATA                                   0	u32		eeclkfreq;	u32		_unused0;	// offset 0x0010	u32		pciirqenb0;		/* interrupt PCI master ... */#define     SETUP_PACKET_INTERRUPT_ENABLE                       7#define     ENDPOINT_F_INTERRUPT_ENABLE                         6#define     ENDPOINT_E_INTERRUPT_ENABLE                         5#define     ENDPOINT_D_INTERRUPT_ENABLE                         4#define     ENDPOINT_C_INTERRUPT_ENABLE                         3#define     ENDPOINT_B_INTERRUPT_ENABLE                         2#define     ENDPOINT_A_INTERRUPT_ENABLE                         1#define     ENDPOINT_0_INTERRUPT_ENABLE                         0	u32		pciirqenb1;#define     PCI_INTERRUPT_ENABLE                                31#define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27#define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26#define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25#define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20#define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19#define     PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE          18#define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17#define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16#define     GPIO_INTERRUPT_ENABLE                               13#define     DMA_D_INTERRUPT_ENABLE                              12#define     DMA_C_INTERRUPT_ENABLE                              11#define     DMA_B_INTERRUPT_ENABLE                              10#define     DMA_A_INTERRUPT_ENABLE                              9#define     EEPROM_DONE_INTERRUPT_ENABLE                        8#define     VBUS_INTERRUPT_ENABLE                               7#define     CONTROL_STATUS_INTERRUPT_ENABLE                     6#define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4#define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3#define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2#define     RESUME_INTERRUPT_ENABLE                             1#define     SOF_INTERRUPT_ENABLE                                0	u32		cpu_irqenb0;		/* ... or onboard 8051 */#define     SETUP_PACKET_INTERRUPT_ENABLE                       7#define     ENDPOINT_F_INTERRUPT_ENABLE                         6#define     ENDPOINT_E_INTERRUPT_ENABLE                         5#define     ENDPOINT_D_INTERRUPT_ENABLE                         4#define     ENDPOINT_C_INTERRUPT_ENABLE                         3#define     ENDPOINT_B_INTERRUPT_ENABLE                         2#define     ENDPOINT_A_INTERRUPT_ENABLE                         1#define     ENDPOINT_0_INTERRUPT_ENABLE                         0	u32		cpu_irqenb1;#define     CPU_INTERRUPT_ENABLE                                31#define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27#define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26#define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25#define     PCI_INTA_INTERRUPT_ENABLE                           24#define     PCI_PME_INTERRUPT_ENABLE                            23#define     PCI_SERR_INTERRUPT_ENABLE                           22#define     PCI_PERR_INTERRUPT_ENABLE                           21#define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20#define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19#define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17#define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16#define     GPIO_INTERRUPT_ENABLE                               13#define     DMA_D_INTERRUPT_ENABLE                              12#define     DMA_C_INTERRUPT_ENABLE                              11#define     DMA_B_INTERRUPT_ENABLE                              10#define     DMA_A_INTERRUPT_ENABLE                              9#define     EEPROM_DONE_INTERRUPT_ENABLE                        8#define     VBUS_INTERRUPT_ENABLE                               7#define     CONTROL_STATUS_INTERRUPT_ENABLE                     6#define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4#define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3#define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2#define     RESUME_INTERRUPT_ENABLE                             1#define     SOF_INTERRUPT_ENABLE                                0	// offset 0x0020	u32		_unused1;	u32		usbirqenb1;#define     USB_INTERRUPT_ENABLE                                31#define     POWER_STATE_CHANGE_INTERRUPT_ENABLE                 27#define     PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                26#define     PCI_PARITY_ERROR_INTERRUPT_ENABLE                   25#define     PCI_INTA_INTERRUPT_ENABLE                           24#define     PCI_PME_INTERRUPT_ENABLE                            23#define     PCI_SERR_INTERRUPT_ENABLE                           22#define     PCI_PERR_INTERRUPT_ENABLE                           21#define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE          20#define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE          19#define     PCI_RETRY_ABORT_INTERRUPT_ENABLE                    17#define     PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE              16#define     GPIO_INTERRUPT_ENABLE                               13#define     DMA_D_INTERRUPT_ENABLE                              12#define     DMA_C_INTERRUPT_ENABLE                              11#define     DMA_B_INTERRUPT_ENABLE                              10#define     DMA_A_INTERRUPT_ENABLE                              9#define     EEPROM_DONE_INTERRUPT_ENABLE                        8#define     VBUS_INTERRUPT_ENABLE                               7#define     CONTROL_STATUS_INTERRUPT_ENABLE                     6#define     ROOT_PORT_RESET_INTERRUPT_ENABLE                    4#define     SUSPEND_REQUEST_INTERRUPT_ENABLE                    3#define     SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE             2#define     RESUME_INTERRUPT_ENABLE                             1#define     SOF_INTERRUPT_ENABLE                                0	u32		irqstat0;#define     INTA_ASSERTED                                       12#define     SETUP_PACKET_INTERRUPT                              7#define     ENDPOINT_F_INTERRUPT                                6#define     ENDPOINT_E_INTERRUPT                                5#define     ENDPOINT_D_INTERRUPT                                4#define     ENDPOINT_C_INTERRUPT                                3#define     ENDPOINT_B_INTERRUPT                                2#define     ENDPOINT_A_INTERRUPT                                1#define     ENDPOINT_0_INTERRUPT                                0	u32		irqstat1;#define     POWER_STATE_CHANGE_INTERRUPT                        27#define     PCI_ARBITER_TIMEOUT_INTERRUPT                       26#define     PCI_PARITY_ERROR_INTERRUPT                          25#define     PCI_INTA_INTERRUPT                                  24#define     PCI_PME_INTERRUPT                                   23#define     PCI_SERR_INTERRUPT                                  22#define     PCI_PERR_INTERRUPT                                  21#define     PCI_MASTER_ABORT_RECEIVED_INTERRUPT                 20#define     PCI_TARGET_ABORT_RECEIVED_INTERRUPT                 19#define     PCI_RETRY_ABORT_INTERRUPT                           17#define     PCI_MASTER_CYCLE_DONE_INTERRUPT                     16#define     GPIO_INTERRUPT                                      13#define     DMA_D_INTERRUPT                                     12#define     DMA_C_INTERRUPT                                     11#define     DMA_B_INTERRUPT                                     10#define     DMA_A_INTERRUPT                                     9#define     EEPROM_DONE_INTERRUPT                               8#define     VBUS_INTERRUPT                                      7#define     CONTROL_STATUS_INTERRUPT                            6#define     ROOT_PORT_RESET_INTERRUPT                           4#define     SUSPEND_REQUEST_INTERRUPT                           3#define     SUSPEND_REQUEST_CHANGE_INTERRUPT                    2#define     RESUME_INTERRUPT                                    1#define     SOF_INTERRUPT                                       0	// offset 0x0030	u32		idxaddr;	u32		idxdata;	u32		fifoctl;#define     PCI_BASE2_RANGE                                     16#define     IGNORE_FIFO_AVAILABILITY                            3#define     PCI_BASE2_SELECT                                    2#define     FIFO_CONFIGURATION_SELECT                           0	u32		_unused2;	// offset 0x0040	u32		memaddr;#define     START                                               28#define     DIRECTION                                           27#define     FIFO_DIAGNOSTIC_SELECT                              24#define     MEMORY_ADDRESS                                      0	u32		memdata0;	u32		memdata1;	u32		_unused3;	// offset 0x0050	u32		gpioctl;#define     GPIO3_LED_SELECT                                    12#define     GPIO3_INTERRUPT_ENABLE                              11#define     GPIO2_INTERRUPT_ENABLE                              10#define     GPIO1_INTERRUPT_ENABLE                              9#define     GPIO0_INTERRUPT_ENABLE                              8#define     GPIO3_OUTPUT_ENABLE                                 7#define     GPIO2_OUTPUT_ENABLE                                 6#define     GPIO1_OUTPUT_ENABLE                                 5#define     GPIO0_OUTPUT_ENABLE                                 4#define     GPIO3_DATA                                          3#define     GPIO2_DATA                                          2#define     GPIO1_DATA                                          1#define     GPIO0_DATA                                          0	u32		gpiostat;#define     GPIO3_INTERRUPT                                     3#define     GPIO2_INTERRUPT                                     2#define     GPIO1_INTERRUPT                                     1#define     GPIO0_INTERRUPT                                     0} __attribute__ ((packed));/* usb control, BAR0 + 0x0080 */struct net2280_usb_regs {	// offset 0x0080	u32		stdrsp;#define     STALL_UNSUPPORTED_REQUESTS                          31#define     SET_TEST_MODE                                       16#define     GET_OTHER_SPEED_CONFIGURATION                       15#define     GET_DEVICE_QUALIFIER                                14#define     SET_ADDRESS                                         13#define     ENDPOINT_SET_CLEAR_HALT                             12#define     DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP               11#define     GET_STRING_DESCRIPTOR_2                             10#define     GET_STRING_DESCRIPTOR_1                             9#define     GET_STRING_DESCRIPTOR_0                             8#define     GET_SET_INTERFACE                                   6#define     GET_SET_CONFIGURATION                               5#define     GET_CONFIGURATION_DESCRIPTOR                        4#define     GET_DEVICE_DESCRIPTOR                               3#define     GET_ENDPOINT_STATUS                                 2