#define T1UFINT_ISR  *((volatile unsigned long *)0x000D5A)   /* EV-A          */
#define T1OFINT_ISR  *((volatile unsigned long *)0x000D5C)   /* EV-A          */
#define REVD2_8      *((volatile unsigned long *)0x000D5E)   /* reserved  */

/*--------- Group 3 PIE Interrupt Service Routines  -------------------*/
#define T2PINT_ISR   *((volatile unsigned long *)0x000D60)   /* EV-A          */
#define T2CINT_ISR   *((volatile unsigned long *)0x000D62)   /* EV-A          */
#define T2UFINT_ISR  *((volatile unsigned long *)0x000D64)   /* EV-A          */
#define T2OFINT_ISR  *((volatile unsigned long *)0x000D66)   /* EV-A          */
#define CAPINT1_ISR  *((volatile unsigned long *)0x000D68)   /* EV-A          */
#define CAPINT2_ISR  *((volatile unsigned long *)0x000D6A)   /* EV-A          */
#define CAPINT3_ISR  *((volatile unsigned long *)0x000D6C)   /* EV-A          */
#define REVD3_8      *((volatile unsigned long *)0x000D6E)   /* reserved  */

/*----------- Group 4 PIE Interrupt Service Routines  --------------*/
#define CMP4INT_ISR  *((volatile unsigned long *)0x000D70)   /* EV-A          */
#define CMP5INT_ISR  *((volatile unsigned long *)0x000D72)   /* EV-A          */
#define CMP6INT_ISR  *((volatile unsigned long *)0x000D74)   /* EV-A          */
#define T3PINT_ISR   *((volatile unsigned long *)0x000D76)   /* EV-A          */
#define T3CINT_ISR   *((volatile unsigned long *)0x000D78)   /* EV-A          */
#define T3UFINT_ISR  *((volatile unsigned long *)0x000D7A)   /* EV-A          */
#define T3OFINT_ISR  *((volatile unsigned long *)0x000D7C)   /* EV-A          */
#define REVD4_8      *((volatile unsigned long *)0x000D7E)   /* reserved  */

/*--------- Group 5 PIE Interrupt Service Routines  -------------------*/
#define T4PINT_ISR   *((volatile unsigned long *)0x000D80)   /* EV-A          */
#define T4CINT_ISR   *((volatile unsigned long *)0x000D82)   /* EV-A          */
#define T4UFINT_ISR  *((volatile unsigned long *)0x000D84)   /* EV-A          */
#define T4OFINT_ISR  *((volatile unsigned long *)0x000D86)   /* EV-A          */
#define CAPINT4_ISR  *((volatile unsigned long *)0x000D88)   /* EV-A          */
#define CAPINT5_ISR  *((volatile unsigned long *)0x000D8A)   /* EV-A          */
#define CAPINT6_ISR  *((volatile unsigned long *)0x000D8C)   /* EV-A          */
#define REVD5_8      *((volatile unsigned long *)0x000D8E)   /* reserved  */

/*--------  Group 6 PIE Interrupt Service Routines   ---------------------*/
#define SPIRXINTA_ISR  *((volatile unsigned long *)0x000D90)   /*  SPI-A  RX */
#define SPITXINTA_ISR  *((volatile unsigned long *)0x000D92)   /*  SPI-A  TX */
#define REVD6_3        *((volatile unsigned long *)0x000D94)   /* reserved  */
#define REVD6_4        *((volatile unsigned long *)0x000D96)   /* reserved  */
#define MRINTA_ISR     *((volatile unsigned long *)0x000D98)   /*  McBSP-A */
#define MXINTA_ISR     *((volatile unsigned long *)0x000D9A)   /*  McBSP-A */
#define REVD6_7        *((volatile unsigned long *)0x000D9C)   /* reserved  */
#define REVD6_8        *((volatile unsigned long *)0x000D9E)   /* reserved  */

/*--------  Group 7 PIE Interrupt Service Routines   ---------------------*/
#define REVD7_1        *((volatile unsigned long *)0x000DA0)   /* reserved  */
#define REVD7_2        *((volatile unsigned long *)0x000DA2)   /* reserved  */
#define REVD7_3        *((volatile unsigned long *)0x000DA4)   /* reserved  */
#define REVD7_4        *((volatile unsigned long *)0x000DA6)   /* reserved  */
#define REVD7_5        *((volatile unsigned long *)0x000DA8)   /* reserved  */
#define REVD7_6        *((volatile unsigned long *)0x000DAA)   /* reserved  */
#define REVD7_7        *((volatile unsigned long *)0x000DAC)   /* reserved  */
#define REVD7_8        *((volatile unsigned long *)0x000DAE)   /* reserved  */

/*--------  Group 8 PIE Interrupt Service Routines   ---------------------*/
#define REVD8_1        *((volatile unsigned long *)0x000DB0)   /* reserved  */
#define REVD8_2        *((volatile unsigned long *)0x000DB2)   /* reserved  */
#define REVD8_3        *((volatile unsigned long *)0x000DB4)   /* reserved  */
#define REVD8_4        *((volatile unsigned long *)0x000DB6)   /* reserved  */
#define REVD8_5        *((volatile unsigned long *)0x000DB8)   /* reserved  */
#define REVD8_6        *((volatile unsigned long *)0x000DBA)   /* reserved  */
#define REVD8_7        *((volatile unsigned long *)0x000DBC)   /* reserved  */
#define REVD8_8        *((volatile unsigned long *)0x000DBE)   /* reserved  */
   
/*---------  Group 9 PIE Interrupt Service Routines  ----------------------*/
#define SCIRXINTA_ISR  *((volatile unsigned long *)0x000DC0)   /*  SCI-A  RX */
#define SCITXINTA_ISR  *((volatile unsigned long *)0x000DC2)   /*  SCI-A  TX */
#define SCIRXINTB_ISR  *((volatile unsigned long *)0x000DC4)   /*  SCI-B  RX */
#define SCITXINTB_ISR  *((volatile unsigned long *)0x000DC6)   /*  SCI-B  TX */
#define ECAN0INTA_ISR  *((volatile unsigned long *)0x000DC8)   /*  eCAN      */
#define ECAN1INTA_ISR  *((volatile unsigned long *)0x000DCA)   /*  eCAN      */
#define REVD9_7        *((volatile unsigned long *)0x000DCC)   /* reserved  */
#define REVD9_8        *((volatile unsigned long *)0x000DCE)   /* reserved  */

/*--------  Group 10 PIE Interrupt Service Routines   ---------------------*/
#define REVD10_1        *((volatile unsigned long *)0x000DD0)   /* reserved  */
#define REVD10_2        *((volatile unsigned long *)0x000DD2)   /* reserved  */
#define REVD10_3        *((volatile unsigned long *)0x000DD4)   /* reserved  */
#define REVD10_4        *((volatile unsigned long *)0x000DD6)   /* reserved  */
#define REVD10_5        *((volatile unsigned long *)0x000DD8)   /* reserved  */
#define REVD10_6        *((volatile unsigned long *)0x000DDA)   /* reserved  */
#define REVD10_7        *((volatile unsigned long *)0x000DDC)   /* reserved  */
#define REVD10_8        *((volatile unsigned long *)0x000DDE)   /* reserved  */

/*--------  Group 11 PIE Interrupt Service Routines   ---------------------*/
#define REVD11_1        *((volatile unsigned long *)0x000DE0)   /* reserved  */
#define REVD11_2        *((volatile unsigned long *)0x000DE2)   /* reserved  */
#define REVD11_3        *((volatile unsigned long *)0x000DE4)   /* reserved  */
#define REVD11_4        *((volatile unsigned long *)0x000DE6)   /* reserved  */
#define REVD11_5        *((volatile unsigned long *)0x000DE8)   /* reserved  */
#define REVD11_6        *((volatile unsigned long *)0x000DEA)   /* reserved  */
#define REVD11_7        *((volatile unsigned long *)0x000DEC)   /* reserved  */
#define REVD11_8        *((volatile unsigned long *)0x000DEE)   /* reserved  */

/*--------  Group 12 PIE Interrupt Service Routines   ---------------------*/
#define REVD12_1        *((volatile unsigned long *)0x000DF0)   /* reserved  */
#define REVD12_2        *((volatile unsigned long *)0x000DF2)   /* reserved  */
#define REVD12_3        *((volatile unsigned long *)0x000DF4)   /* reserved  */
#define REVD12_4        *((volatile unsigned long *)0x000DF6)   /* reserved  */
#define REVD12_5        *((volatile unsigned long *)0x000DF8)   /* reserved  */
#define REVD12_6        *((volatile unsigned long *)0x000DFA)   /* reserved  */
#define REVD12_7        *((volatile unsigned long *)0x000DFC)   /* reserved  */
#define REVD12_8        *((volatile unsigned long *)0x000DFE)   /* reserved  */



/*============   CPU-Timers 0, 1, 2 Configuration and Control Registers    =============*/

#define TIMER0TIM   *((volatile unsigned long *)0x000C00)   /* CPU-Timer 0, Counter Register 32bits */
#define TIMER0TIML  *((volatile unsigned int *)0x000C00)    /* CPU-Timer 0, Counter Register Low  */
#define TIMER0TIMH  *((volatile unsigned int *)0x000C01)    /* CPU-Timer 0, Counter Register High */

#define TIMER0PRD   *((volatile unsigned long *)0x000C02)    /*  CPU-Timer 0, Period Register 32bits */
#define TIMER0PRDL  *((volatile unsigned int *)0x000C02)    /*  CPU-Timer 0, Period Register Low */
#define TIMER0PRDH  *((volatile unsigned int *)0x000C03)    /*  CPU-Timer 0, Period Register High */


#define TIMER0TCR   *((volatile unsigned int *)0x000C04)    /*  CPU-Timer 0, Control Register  */
  
  /*  reserved   0x000C05    */

#define TIMER0TPR   *((volatile unsigned long *)0x000C06)   /*  CPU-Timer 0, Prescale Register 32bits */
#define TIMER0TPRL  *((volatile unsigned int *)0x000C06)    /*  CPU-Timer 0, Prescale Register Low  */
#define TIMER0TPRH  *((volatile unsigned int *)0x000C07)    /*  CPU-Timer 0, Prescale Register High  */


#define TIMER1TIM   *((volatile unsigned long *)0x000C08)    /*  CPU-Timer 1, Counter Register 32bits  */
#define TIMER1TIML  *((volatile unsigned int *)0x000C08)    /*  CPU-Timer 1, Counter Register Low  */
#define TIMER1TIMH  *((volatile unsigned int *)0x000C09)    /*  CPU-Timer 1, Counter Register High */

#define TIMER1PRD   *((volatile unsigned long *)0x000C0A)    /* CPU-Timer 1, Period Register 32bits  */
#define TIMER1PRDL  *((volatile unsigned int *)0x000C0A)    /* CPU-Timer 1, Period Register  Low  */
#define TIMER1PRDH  *((volatile unsigned int *)0x000C0B)    /* CPU-Timer 1, Period Register High  */

#define TIMER1TCR   *((volatile unsigned int *)0x000C0C）   /* CPU-Timer 1, Control Register   */

   /*   reserved 0x00 0C0D   */
#define TIMER1TPR   *((volatile unsigned long *)0x000C0E)   /* CPU-Timer 1, Prescale Register 32bits */
#define TIMER1TPRL  *((volatile unsigned int *)0x000C0E)    /* CPU-Timer 1, Prescale Register Low */
#define TIMER1TPRH  *((volatile unsigned int *)0x000C0F)    /* CPU-Timer 1, Prescale Register High  */


#define TIMER2TIM   *((volatile unsigned long *)0x000C10)  /* CPU-Timer 2, Counter Register 32bits */
#define TIMER2TIML  *((volatile unsigned int *)0x000C10)   /* CPU-Timer 2, Counter Register Low */
#define TIMER2TIMH  *((volatile unsigned int *)0x000C11)   /* CPU-Timer 2, Counter Register High */

#define TIMER2PRD   *((volatile unsigned long *)0x000C12)  /* CPU-Timer 2, Period Register 32bits  */
#define TIMER2PRDL  *((volatile unsigned int *)0x000C12)   /* CPU-Timer 2, Period Register Low  */
#define TIMER2PRDH  *((volatile unsigned int *)0x000C13)   /* CPU-Timer 2, Period Register High */

#define TIMER2TCR   *((volatile unsigned int *)0x000C14)   /* CPU-Timer 2, Control Register  */
   
    /*    reserved 0x00 0C15   */

#define TIMER2TPR   *((volatile unsigned long *)0x000C16)   /* CPU-Timer 2, Prescale Register 32bits */
#define TIMER2TPRL  *((volatile unsigned int *)0x000C16)    /* CPU-Timer 2, Prescale Register Low */
#define TIMER2TPRH  *((volatile unsigned int *)0x000C17)    /* CPU-Timer 2, Prescale Register High */

  /*  0x000C18 ~ 0x000C3F 40  reserved  */