J1_ram_block2a11_PORT_A_write_enable_reg = DFFE(J1_ram_block2a11_PORT_A_write_enable, J1_ram_block2a11_clock_0, , , );
J1_ram_block2a11_PORT_B_read_enable = VCC;
J1_ram_block2a11_PORT_B_read_enable_reg = DFFE(J1_ram_block2a11_PORT_B_read_enable, J1_ram_block2a11_clock_1, , , J1_ram_block2a11_clock_enable_1);
J1_ram_block2a11_clock_0 = clock;
J1_ram_block2a11_clock_1 = clock;
J1_ram_block2a11_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a11_PORT_B_data_out = MEMORY(J1_ram_block2a11_PORT_A_data_in_reg, , J1_ram_block2a11_PORT_A_address_reg, J1_ram_block2a11_PORT_B_address_reg, J1_ram_block2a11_PORT_A_write_enable_reg, J1_ram_block2a11_PORT_B_read_enable_reg, , , J1_ram_block2a11_clock_0, J1_ram_block2a11_clock_1, , J1_ram_block2a11_clock_enable_1, , );
J1_ram_block2a11 = J1_ram_block2a11_PORT_B_data_out[0];


--J1_ram_block2a12 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a12
J1_ram_block2a12_PORT_A_data_in = data[4];
J1_ram_block2a12_PORT_A_data_in_reg = DFFE(J1_ram_block2a12_PORT_A_data_in, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a12_PORT_A_address_reg = DFFE(J1_ram_block2a12_PORT_A_address, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a12_PORT_B_address_reg = DFFE(J1_ram_block2a12_PORT_B_address, J1_ram_block2a12_clock_1, , , J1_ram_block2a12_clock_enable_1);
J1_ram_block2a12_PORT_A_write_enable = K1L2;
J1_ram_block2a12_PORT_A_write_enable_reg = DFFE(J1_ram_block2a12_PORT_A_write_enable, J1_ram_block2a12_clock_0, , , );
J1_ram_block2a12_PORT_B_read_enable = VCC;
J1_ram_block2a12_PORT_B_read_enable_reg = DFFE(J1_ram_block2a12_PORT_B_read_enable, J1_ram_block2a12_clock_1, , , J1_ram_block2a12_clock_enable_1);
J1_ram_block2a12_clock_0 = clock;
J1_ram_block2a12_clock_1 = clock;
J1_ram_block2a12_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a12_PORT_B_data_out = MEMORY(J1_ram_block2a12_PORT_A_data_in_reg, , J1_ram_block2a12_PORT_A_address_reg, J1_ram_block2a12_PORT_B_address_reg, J1_ram_block2a12_PORT_A_write_enable_reg, J1_ram_block2a12_PORT_B_read_enable_reg, , , J1_ram_block2a12_clock_0, J1_ram_block2a12_clock_1, , J1_ram_block2a12_clock_enable_1, , );
J1_ram_block2a12 = J1_ram_block2a12_PORT_B_data_out[0];


--J1_ram_block2a13 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a13
J1_ram_block2a13_PORT_A_data_in = data[5];
J1_ram_block2a13_PORT_A_data_in_reg = DFFE(J1_ram_block2a13_PORT_A_data_in, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a13_PORT_A_address_reg = DFFE(J1_ram_block2a13_PORT_A_address, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a13_PORT_B_address_reg = DFFE(J1_ram_block2a13_PORT_B_address, J1_ram_block2a13_clock_1, , , J1_ram_block2a13_clock_enable_1);
J1_ram_block2a13_PORT_A_write_enable = K1L2;
J1_ram_block2a13_PORT_A_write_enable_reg = DFFE(J1_ram_block2a13_PORT_A_write_enable, J1_ram_block2a13_clock_0, , , );
J1_ram_block2a13_PORT_B_read_enable = VCC;
J1_ram_block2a13_PORT_B_read_enable_reg = DFFE(J1_ram_block2a13_PORT_B_read_enable, J1_ram_block2a13_clock_1, , , J1_ram_block2a13_clock_enable_1);
J1_ram_block2a13_clock_0 = clock;
J1_ram_block2a13_clock_1 = clock;
J1_ram_block2a13_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a13_PORT_B_data_out = MEMORY(J1_ram_block2a13_PORT_A_data_in_reg, , J1_ram_block2a13_PORT_A_address_reg, J1_ram_block2a13_PORT_B_address_reg, J1_ram_block2a13_PORT_A_write_enable_reg, J1_ram_block2a13_PORT_B_read_enable_reg, , , J1_ram_block2a13_clock_0, J1_ram_block2a13_clock_1, , J1_ram_block2a13_clock_enable_1, , );
J1_ram_block2a13 = J1_ram_block2a13_PORT_B_data_out[0];


--J1_ram_block2a14 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a14
J1_ram_block2a14_PORT_A_data_in = data[6];
J1_ram_block2a14_PORT_A_data_in_reg = DFFE(J1_ram_block2a14_PORT_A_data_in, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a14_PORT_A_address_reg = DFFE(J1_ram_block2a14_PORT_A_address, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a14_PORT_B_address_reg = DFFE(J1_ram_block2a14_PORT_B_address, J1_ram_block2a14_clock_1, , , J1_ram_block2a14_clock_enable_1);
J1_ram_block2a14_PORT_A_write_enable = K1L2;
J1_ram_block2a14_PORT_A_write_enable_reg = DFFE(J1_ram_block2a14_PORT_A_write_enable, J1_ram_block2a14_clock_0, , , );
J1_ram_block2a14_PORT_B_read_enable = VCC;
J1_ram_block2a14_PORT_B_read_enable_reg = DFFE(J1_ram_block2a14_PORT_B_read_enable, J1_ram_block2a14_clock_1, , , J1_ram_block2a14_clock_enable_1);
J1_ram_block2a14_clock_0 = clock;
J1_ram_block2a14_clock_1 = clock;
J1_ram_block2a14_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a14_PORT_B_data_out = MEMORY(J1_ram_block2a14_PORT_A_data_in_reg, , J1_ram_block2a14_PORT_A_address_reg, J1_ram_block2a14_PORT_B_address_reg, J1_ram_block2a14_PORT_A_write_enable_reg, J1_ram_block2a14_PORT_B_read_enable_reg, , , J1_ram_block2a14_clock_0, J1_ram_block2a14_clock_1, , J1_ram_block2a14_clock_enable_1, , );
J1_ram_block2a14 = J1_ram_block2a14_PORT_B_data_out[0];


--J1_ram_block2a15 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a15
J1_ram_block2a15_PORT_A_data_in = data[7];
J1_ram_block2a15_PORT_A_data_in_reg = DFFE(J1_ram_block2a15_PORT_A_data_in, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a15_PORT_A_address_reg = DFFE(J1_ram_block2a15_PORT_A_address, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a15_PORT_B_address_reg = DFFE(J1_ram_block2a15_PORT_B_address, J1_ram_block2a15_clock_1, , , J1_ram_block2a15_clock_enable_1);
J1_ram_block2a15_PORT_A_write_enable = K1L2;
J1_ram_block2a15_PORT_A_write_enable_reg = DFFE(J1_ram_block2a15_PORT_A_write_enable, J1_ram_block2a15_clock_0, , , );
J1_ram_block2a15_PORT_B_read_enable = VCC;
J1_ram_block2a15_PORT_B_read_enable_reg = DFFE(J1_ram_block2a15_PORT_B_read_enable, J1_ram_block2a15_clock_1, , , J1_ram_block2a15_clock_enable_1);
J1_ram_block2a15_clock_0 = clock;
J1_ram_block2a15_clock_1 = clock;
J1_ram_block2a15_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a15_PORT_B_data_out = MEMORY(J1_ram_block2a15_PORT_A_data_in_reg, , J1_ram_block2a15_PORT_A_address_reg, J1_ram_block2a15_PORT_B_address_reg, J1_ram_block2a15_PORT_A_write_enable_reg, J1_ram_block2a15_PORT_B_read_enable_reg, , , J1_ram_block2a15_clock_0, J1_ram_block2a15_clock_1, , J1_ram_block2a15_clock_enable_1, , );
J1_ram_block2a15 = J1_ram_block2a15_PORT_B_data_out[0];


--H1_safe_q[12] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[12]
--operation mode is normal

H1_safe_q[12]_carry_eqn = H1L52;
H1_safe_q[12]_lut_out = H1_safe_q[12] $ !H1_safe_q[12]_carry_eqn;
H1_safe_q[12] = DFFEA(H1_safe_q[12]_lut_out, clock, VCC, , E1L1, , );


--H1_safe_q[11] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[11]
--operation mode is arithmetic

H1_safe_q[11]_carry_eqn = H1L32;
H1_safe_q[11]_lut_out = H1_safe_q[11] $ H1_safe_q[11]_carry_eqn;
H1_safe_q[11] = DFFEA(H1_safe_q[11]_lut_out, clock, VCC, , E1L1, , );

--H1L52 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[11]~COUT
--operation mode is arithmetic

H1L52 = CARRY(H1_safe_q[11] $ D1_valid_wreq # !H1L32);


--H1_safe_q[10] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[10]
--operation mode is arithmetic

H1_safe_q[10]_carry_eqn = H1L12;
H1_safe_q[10]_lut_out = H1_safe_q[10] $ !H1_safe_q[10]_carry_eqn;
H1_safe_q[10] = DFFEA(H1_safe_q[10]_lut_out, clock, VCC, , E1L1, , );

--H1L32 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[10]~COUT
--operation mode is arithmetic

H1L32 = CARRY(!H1L12 & (H1_safe_q[10] $ !D1_valid_wreq));


--H1_safe_q[9] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[9]
--operation mode is arithmetic

H1_safe_q[9]_carry_eqn = H1L91;
H1_safe_q[9]_lut_out = H1_safe_q[9] $ H1_safe_q[9]_carry_eqn;
H1_safe_q[9] = DFFEA(H1_safe_q[9]_lut_out, clock, VCC, , E1L1, , );

--H1L12 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[9]~COUT
--operation mode is arithmetic

H1L12 = CARRY(H1_safe_q[9] $ D1_valid_wreq # !H1L91);


--H1_safe_q[8] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[8]
--operation mode is arithmetic

H1_safe_q[8]_carry_eqn = H1L71;
H1_safe_q[8]_lut_out = H1_safe_q[8] $ !H1_safe_q[8]_carry_eqn;
H1_safe_q[8] = DFFEA(H1_safe_q[8]_lut_out, clock, VCC, , E1L1, , );

--H1L91 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[8]~COUT
--operation mode is arithmetic

H1L91 = CARRY(!H1L71 & (H1_safe_q[8] $ !D1_valid_wreq));


--H1_safe_q[7] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[7]
--operation mode is arithmetic

H1_safe_q[7]_carry_eqn = H1L51;
H1_safe_q[7]_lut_out = H1_safe_q[7] $ H1_safe_q[7]_carry_eqn;
H1_safe_q[7] = DFFEA(H1_safe_q[7]_lut_out, clock, VCC, , E1L1, , );

--H1L71 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[7]~COUT
--operation mode is arithmetic

H1L71 = CARRY(H1_safe_q[7] $ D1_valid_wreq # !H1L51);


--H1_safe_q[6] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[6]
--operation mode is arithmetic

H1_safe_q[6]_carry_eqn = H1L31;
H1_safe_q[6]_lut_out = H1_safe_q[6] $ !H1_safe_q[6]_carry_eqn;
H1_safe_q[6] = DFFEA(H1_safe_q[6]_lut_out, clock, VCC, , E1L1, , );

--H1L51 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[6]~COUT
--operation mode is arithmetic

H1L51 = CARRY(!H1L31 & (H1_safe_q[6] $ !D1_valid_wreq));


--H1_safe_q[5] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[5]
--operation mode is arithmetic

H1_safe_q[5]_carry_eqn = H1L11;
H1_safe_q[5]_lut_out = H1_safe_q[5] $ H1_safe_q[5]_carry_eqn;
H1_safe_q[5] = DFFEA(H1_safe_q[5]_lut_out, clock, VCC, , E1L1, , );

--H1L31 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[5]~COUT
--operation mode is arithmetic

H1L31 = CARRY(H1_safe_q[5] $ D1_valid_wreq # !H1L11);


--H1_safe_q[4] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[4]
--operation mode is arithmetic

H1_safe_q[4]_carry_eqn = H1L9;
H1_safe_q[4]_lut_out = H1_safe_q[4] $ !H1_safe_q[4]_carry_eqn;
H1_safe_q[4] = DFFEA(H1_safe_q[4]_lut_out, clock, VCC, , E1L1, , );

--H1L11 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[4]~COUT
--operation mode is arithmetic

H1L11 = CARRY(!H1L9 & (H1_safe_q[4] $ !D1_valid_wreq));


--H1_safe_q[3] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3]
--operation mode is arithmetic

H1_safe_q[3]_carry_eqn = H1L7;
H1_safe_q[3]_lut_out = H1_safe_q[3] $ H1_safe_q[3]_carry_eqn;
H1_safe_q[3] = DFFEA(H1_safe_q[3]_lut_out, clock, VCC, , E1L1, , );

--H1L9 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[3]~COUT
--operation mode is arithmetic

H1L9 = CARRY(H1_safe_q[3] $ D1_valid_wreq # !H1L7);


--H1_safe_q[2] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]
--operation mode is arithmetic

H1_safe_q[2]_carry_eqn = H1L5;
H1_safe_q[2]_lut_out = H1_safe_q[2] $ !H1_safe_q[2]_carry_eqn;
H1_safe_q[2] = DFFEA(H1_safe_q[2]_lut_out, clock, VCC, , E1L1, , );

--H1L7 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[2]~COUT
--operation mode is arithmetic

H1L7 = CARRY(!H1L5 & (H1_safe_q[2] $ !D1_valid_wreq));


--H1_safe_q[1] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]
--operation mode is arithmetic

H1_safe_q[1]_carry_eqn = H1L3;
H1_safe_q[1]_lut_out = H1_safe_q[1] $ H1_safe_q[1]_carry_eqn;
H1_safe_q[1] = DFFEA(H1_safe_q[1]_lut_out, clock, VCC, , E1L1, , );

--H1L5 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[1]~COUT
--operation mode is arithmetic

H1L5 = CARRY(H1_safe_q[1] $ D1_valid_wreq # !H1L3);


--H1_safe_q[0] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]
--operation mode is arithmetic

H1_safe_q[0]_lut_out = !H1_safe_q[0];
H1_safe_q[0] = DFFEA(H1_safe_q[0]_lut_out, clock, VCC, , E1L1, , );

--H1L3 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|a_fefifo_n4f:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT
--operation mode is arithmetic

H1L3 = CARRY(H1_safe_q[0] $ !D1_valid_wreq);


--J1_address_reg_b[0] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|address_reg_b[0]
--operation mode is normal

J1_address_reg_b[0]_lut_out = H2_safe_q[12];
J1_address_reg_b[0] = DFFEA(J1_address_reg_b[0]_lut_out, clock, VCC, , D1_valid_rreq, , );


--L1L8 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result399w~10
--operation mode is normal

L1L8 = J1_ram_block2a15 & (J1_ram_block2a7 # J1_address_reg_b[0]) # !J1_ram_block2a15 & J1_ram_block2a7 & !J1_address_reg_b[0];


--L1L7 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result387w~10
--operation mode is normal

L1L7 = J1_ram_block2a14 & (J1_ram_block2a6 # J1_address_reg_b[0]) # !J1_ram_block2a14 & J1_ram_block2a6 & !J1_address_reg_b[0];


--L1L6 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|mux_kl7:mux4|w_result375w~10
--operation mode is normal