--H2_safe_q[2] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X17_Y23_N6
--operation mode is arithmetic

H2_safe_q[2]_carry_eqn = (!H2L3 & H2L03) # (H2L3 & H2L13);
H2_safe_q[2]_lut_out = H2_safe_q[2] $ (D1_valid_rreq & !H2_safe_q[2]_carry_eqn);
H2_safe_q[2] = DFFEA(H2_safe_q[2]_lut_out, GLOBAL(clock), VCC, , , , );

--H2L33 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X17_Y23_N6
--operation mode is arithmetic

H2L33_cout_0 = H2_safe_q[2] & !H2L03;
H2L33 = CARRY(H2L33_cout_0);

--H2L43 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X17_Y23_N6
--operation mode is arithmetic

H2L43_cout_1 = H2_safe_q[2] & !H2L13;
H2L43 = CARRY(H2L43_cout_1);


--H2_safe_q[1] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X17_Y23_N5
--operation mode is arithmetic

H2_safe_q[1]_carry_eqn = H2L3;
H2_safe_q[1]_lut_out = H2_safe_q[1] $ (D1_valid_rreq & H2_safe_q[1]_carry_eqn);
H2_safe_q[1] = DFFEA(H2_safe_q[1]_lut_out, GLOBAL(clock), VCC, , , , );

--H2L03 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X17_Y23_N5
--operation mode is arithmetic

H2L03_cout_0 = !H2L3 # !H2_safe_q[1];
H2L03 = CARRY(H2L03_cout_0);

--H2L13 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X17_Y23_N5
--operation mode is arithmetic

H2L13_cout_1 = !H2L3 # !H2_safe_q[1];
H2L13 = CARRY(H2L13_cout_1);


--H2_safe_q[0] is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X17_Y23_N4
--operation mode is arithmetic

H2_safe_q[0]_lut_out = D1_valid_rreq $ H2_safe_q[0];
H2_safe_q[0] = DFFEA(H2_safe_q[0]_lut_out, GLOBAL(clock), VCC, , , , );

--H2L3 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|counter_cell[0]~COUT at LC_X17_Y23_N4
--operation mode is arithmetic

H2L3 = CARRY(H2_safe_q[0]);


--J1_ram_block2a0 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a0 at M4K_X15_Y19
J1_ram_block2a0_PORT_A_data_in = data[0];
J1_ram_block2a0_PORT_A_data_in_reg = DFFE(J1_ram_block2a0_PORT_A_data_in, J1_ram_block2a0_clock_0, , , );
J1_ram_block2a0_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a0_PORT_A_address_reg = DFFE(J1_ram_block2a0_PORT_A_address, J1_ram_block2a0_clock_0, , , );
J1_ram_block2a0_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a0_PORT_B_address_reg = DFFE(J1_ram_block2a0_PORT_B_address, J1_ram_block2a0_clock_1, , , J1_ram_block2a0_clock_enable_1);
J1_ram_block2a0_PORT_A_write_enable = K1L1;
J1_ram_block2a0_PORT_A_write_enable_reg = DFFE(J1_ram_block2a0_PORT_A_write_enable, J1_ram_block2a0_clock_0, , , );
J1_ram_block2a0_PORT_B_read_enable = VCC;
J1_ram_block2a0_PORT_B_read_enable_reg = DFFE(J1_ram_block2a0_PORT_B_read_enable, J1_ram_block2a0_clock_1, , , J1_ram_block2a0_clock_enable_1);
J1_ram_block2a0_clock_0 = GLOBAL(clock);
J1_ram_block2a0_clock_1 = GLOBAL(clock);
J1_ram_block2a0_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a0_PORT_B_data_out = MEMORY(J1_ram_block2a0_PORT_A_data_in_reg, , J1_ram_block2a0_PORT_A_address_reg, J1_ram_block2a0_PORT_B_address_reg, J1_ram_block2a0_PORT_A_write_enable_reg, J1_ram_block2a0_PORT_B_read_enable_reg, , , J1_ram_block2a0_clock_0, J1_ram_block2a0_clock_1, , J1_ram_block2a0_clock_enable_1, , );
J1_ram_block2a0 = J1_ram_block2a0_PORT_B_data_out[0];


--J1_ram_block2a1 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a1 at M4K_X15_Y25
J1_ram_block2a1_PORT_A_data_in = data[1];
J1_ram_block2a1_PORT_A_data_in_reg = DFFE(J1_ram_block2a1_PORT_A_data_in, J1_ram_block2a1_clock_0, , , );
J1_ram_block2a1_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a1_PORT_A_address_reg = DFFE(J1_ram_block2a1_PORT_A_address, J1_ram_block2a1_clock_0, , , );
J1_ram_block2a1_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a1_PORT_B_address_reg = DFFE(J1_ram_block2a1_PORT_B_address, J1_ram_block2a1_clock_1, , , J1_ram_block2a1_clock_enable_1);
J1_ram_block2a1_PORT_A_write_enable = K1L1;
J1_ram_block2a1_PORT_A_write_enable_reg = DFFE(J1_ram_block2a1_PORT_A_write_enable, J1_ram_block2a1_clock_0, , , );
J1_ram_block2a1_PORT_B_read_enable = VCC;
J1_ram_block2a1_PORT_B_read_enable_reg = DFFE(J1_ram_block2a1_PORT_B_read_enable, J1_ram_block2a1_clock_1, , , J1_ram_block2a1_clock_enable_1);
J1_ram_block2a1_clock_0 = GLOBAL(clock);
J1_ram_block2a1_clock_1 = GLOBAL(clock);
J1_ram_block2a1_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a1_PORT_B_data_out = MEMORY(J1_ram_block2a1_PORT_A_data_in_reg, , J1_ram_block2a1_PORT_A_address_reg, J1_ram_block2a1_PORT_B_address_reg, J1_ram_block2a1_PORT_A_write_enable_reg, J1_ram_block2a1_PORT_B_read_enable_reg, , , J1_ram_block2a1_clock_0, J1_ram_block2a1_clock_1, , J1_ram_block2a1_clock_enable_1, , );
J1_ram_block2a1 = J1_ram_block2a1_PORT_B_data_out[0];


--J1_ram_block2a2 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a2 at M4K_X15_Y26
J1_ram_block2a2_PORT_A_data_in = data[2];
J1_ram_block2a2_PORT_A_data_in_reg = DFFE(J1_ram_block2a2_PORT_A_data_in, J1_ram_block2a2_clock_0, , , );
J1_ram_block2a2_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a2_PORT_A_address_reg = DFFE(J1_ram_block2a2_PORT_A_address, J1_ram_block2a2_clock_0, , , );
J1_ram_block2a2_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a2_PORT_B_address_reg = DFFE(J1_ram_block2a2_PORT_B_address, J1_ram_block2a2_clock_1, , , J1_ram_block2a2_clock_enable_1);
J1_ram_block2a2_PORT_A_write_enable = K1L1;
J1_ram_block2a2_PORT_A_write_enable_reg = DFFE(J1_ram_block2a2_PORT_A_write_enable, J1_ram_block2a2_clock_0, , , );
J1_ram_block2a2_PORT_B_read_enable = VCC;
J1_ram_block2a2_PORT_B_read_enable_reg = DFFE(J1_ram_block2a2_PORT_B_read_enable, J1_ram_block2a2_clock_1, , , J1_ram_block2a2_clock_enable_1);
J1_ram_block2a2_clock_0 = GLOBAL(clock);
J1_ram_block2a2_clock_1 = GLOBAL(clock);
J1_ram_block2a2_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a2_PORT_B_data_out = MEMORY(J1_ram_block2a2_PORT_A_data_in_reg, , J1_ram_block2a2_PORT_A_address_reg, J1_ram_block2a2_PORT_B_address_reg, J1_ram_block2a2_PORT_A_write_enable_reg, J1_ram_block2a2_PORT_B_read_enable_reg, , , J1_ram_block2a2_clock_0, J1_ram_block2a2_clock_1, , J1_ram_block2a2_clock_enable_1, , );
J1_ram_block2a2 = J1_ram_block2a2_PORT_B_data_out[0];


--J1_ram_block2a3 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a3 at M4K_X15_Y28
J1_ram_block2a3_PORT_A_data_in = data[3];
J1_ram_block2a3_PORT_A_data_in_reg = DFFE(J1_ram_block2a3_PORT_A_data_in, J1_ram_block2a3_clock_0, , , );
J1_ram_block2a3_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a3_PORT_A_address_reg = DFFE(J1_ram_block2a3_PORT_A_address, J1_ram_block2a3_clock_0, , , );
J1_ram_block2a3_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a3_PORT_B_address_reg = DFFE(J1_ram_block2a3_PORT_B_address, J1_ram_block2a3_clock_1, , , J1_ram_block2a3_clock_enable_1);
J1_ram_block2a3_PORT_A_write_enable = K1L1;
J1_ram_block2a3_PORT_A_write_enable_reg = DFFE(J1_ram_block2a3_PORT_A_write_enable, J1_ram_block2a3_clock_0, , , );
J1_ram_block2a3_PORT_B_read_enable = VCC;
J1_ram_block2a3_PORT_B_read_enable_reg = DFFE(J1_ram_block2a3_PORT_B_read_enable, J1_ram_block2a3_clock_1, , , J1_ram_block2a3_clock_enable_1);
J1_ram_block2a3_clock_0 = GLOBAL(clock);
J1_ram_block2a3_clock_1 = GLOBAL(clock);
J1_ram_block2a3_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a3_PORT_B_data_out = MEMORY(J1_ram_block2a3_PORT_A_data_in_reg, , J1_ram_block2a3_PORT_A_address_reg, J1_ram_block2a3_PORT_B_address_reg, J1_ram_block2a3_PORT_A_write_enable_reg, J1_ram_block2a3_PORT_B_read_enable_reg, , , J1_ram_block2a3_clock_0, J1_ram_block2a3_clock_1, , J1_ram_block2a3_clock_enable_1, , );
J1_ram_block2a3 = J1_ram_block2a3_PORT_B_data_out[0];


--J1_ram_block2a4 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a4 at M4K_X15_Y18
J1_ram_block2a4_PORT_A_data_in = data[4];
J1_ram_block2a4_PORT_A_data_in_reg = DFFE(J1_ram_block2a4_PORT_A_data_in, J1_ram_block2a4_clock_0, , , );
J1_ram_block2a4_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a4_PORT_A_address_reg = DFFE(J1_ram_block2a4_PORT_A_address, J1_ram_block2a4_clock_0, , , );
J1_ram_block2a4_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a4_PORT_B_address_reg = DFFE(J1_ram_block2a4_PORT_B_address, J1_ram_block2a4_clock_1, , , J1_ram_block2a4_clock_enable_1);
J1_ram_block2a4_PORT_A_write_enable = K1L1;
J1_ram_block2a4_PORT_A_write_enable_reg = DFFE(J1_ram_block2a4_PORT_A_write_enable, J1_ram_block2a4_clock_0, , , );
J1_ram_block2a4_PORT_B_read_enable = VCC;
J1_ram_block2a4_PORT_B_read_enable_reg = DFFE(J1_ram_block2a4_PORT_B_read_enable, J1_ram_block2a4_clock_1, , , J1_ram_block2a4_clock_enable_1);
J1_ram_block2a4_clock_0 = GLOBAL(clock);
J1_ram_block2a4_clock_1 = GLOBAL(clock);
J1_ram_block2a4_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a4_PORT_B_data_out = MEMORY(J1_ram_block2a4_PORT_A_data_in_reg, , J1_ram_block2a4_PORT_A_address_reg, J1_ram_block2a4_PORT_B_address_reg, J1_ram_block2a4_PORT_A_write_enable_reg, J1_ram_block2a4_PORT_B_read_enable_reg, , , J1_ram_block2a4_clock_0, J1_ram_block2a4_clock_1, , J1_ram_block2a4_clock_enable_1, , );
J1_ram_block2a4 = J1_ram_block2a4_PORT_B_data_out[0];


--J1_ram_block2a5 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a5 at M4K_X15_Y24
J1_ram_block2a5_PORT_A_data_in = data[5];
J1_ram_block2a5_PORT_A_data_in_reg = DFFE(J1_ram_block2a5_PORT_A_data_in, J1_ram_block2a5_clock_0, , , );
J1_ram_block2a5_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a5_PORT_A_address_reg = DFFE(J1_ram_block2a5_PORT_A_address, J1_ram_block2a5_clock_0, , , );
J1_ram_block2a5_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a5_PORT_B_address_reg = DFFE(J1_ram_block2a5_PORT_B_address, J1_ram_block2a5_clock_1, , , J1_ram_block2a5_clock_enable_1);
J1_ram_block2a5_PORT_A_write_enable = K1L1;
J1_ram_block2a5_PORT_A_write_enable_reg = DFFE(J1_ram_block2a5_PORT_A_write_enable, J1_ram_block2a5_clock_0, , , );
J1_ram_block2a5_PORT_B_read_enable = VCC;
J1_ram_block2a5_PORT_B_read_enable_reg = DFFE(J1_ram_block2a5_PORT_B_read_enable, J1_ram_block2a5_clock_1, , , J1_ram_block2a5_clock_enable_1);
J1_ram_block2a5_clock_0 = GLOBAL(clock);
J1_ram_block2a5_clock_1 = GLOBAL(clock);
J1_ram_block2a5_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a5_PORT_B_data_out = MEMORY(J1_ram_block2a5_PORT_A_data_in_reg, , J1_ram_block2a5_PORT_A_address_reg, J1_ram_block2a5_PORT_B_address_reg, J1_ram_block2a5_PORT_A_write_enable_reg, J1_ram_block2a5_PORT_B_read_enable_reg, , , J1_ram_block2a5_clock_0, J1_ram_block2a5_clock_1, , J1_ram_block2a5_clock_enable_1, , );
J1_ram_block2a5 = J1_ram_block2a5_PORT_B_data_out[0];


--J1_ram_block2a6 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a6 at M4K_X15_Y17
J1_ram_block2a6_PORT_A_data_in = data[6];
J1_ram_block2a6_PORT_A_data_in_reg = DFFE(J1_ram_block2a6_PORT_A_data_in, J1_ram_block2a6_clock_0, , , );
J1_ram_block2a6_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a6_PORT_A_address_reg = DFFE(J1_ram_block2a6_PORT_A_address, J1_ram_block2a6_clock_0, , , );
J1_ram_block2a6_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a6_PORT_B_address_reg = DFFE(J1_ram_block2a6_PORT_B_address, J1_ram_block2a6_clock_1, , , J1_ram_block2a6_clock_enable_1);
J1_ram_block2a6_PORT_A_write_enable = K1L1;
J1_ram_block2a6_PORT_A_write_enable_reg = DFFE(J1_ram_block2a6_PORT_A_write_enable, J1_ram_block2a6_clock_0, , , );
J1_ram_block2a6_PORT_B_read_enable = VCC;
J1_ram_block2a6_PORT_B_read_enable_reg = DFFE(J1_ram_block2a6_PORT_B_read_enable, J1_ram_block2a6_clock_1, , , J1_ram_block2a6_clock_enable_1);
J1_ram_block2a6_clock_0 = GLOBAL(clock);
J1_ram_block2a6_clock_1 = GLOBAL(clock);
J1_ram_block2a6_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a6_PORT_B_data_out = MEMORY(J1_ram_block2a6_PORT_A_data_in_reg, , J1_ram_block2a6_PORT_A_address_reg, J1_ram_block2a6_PORT_B_address_reg, J1_ram_block2a6_PORT_A_write_enable_reg, J1_ram_block2a6_PORT_B_read_enable_reg, , , J1_ram_block2a6_clock_0, J1_ram_block2a6_clock_1, , J1_ram_block2a6_clock_enable_1, , );
J1_ram_block2a6 = J1_ram_block2a6_PORT_B_data_out[0];


--J1_ram_block2a7 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a7 at M4K_X15_Y22
J1_ram_block2a7_PORT_A_data_in = data[7];
J1_ram_block2a7_PORT_A_data_in_reg = DFFE(J1_ram_block2a7_PORT_A_data_in, J1_ram_block2a7_clock_0, , , );
J1_ram_block2a7_PORT_A_address = BUS(H3_safe_q[0], H3_safe_q[1], H3_safe_q[2], H3_safe_q[3], H3_safe_q[4], H3_safe_q[5], H3_safe_q[6], H3_safe_q[7], H3_safe_q[8], H3_safe_q[9], H3_safe_q[10], H3_safe_q[11]);
J1_ram_block2a7_PORT_A_address_reg = DFFE(J1_ram_block2a7_PORT_A_address, J1_ram_block2a7_clock_0, , , );
J1_ram_block2a7_PORT_B_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6], H2_safe_q[7], H2_safe_q[8], H2_safe_q[9], H2_safe_q[10], H2_safe_q[11]);
J1_ram_block2a7_PORT_B_address_reg = DFFE(J1_ram_block2a7_PORT_B_address, J1_ram_block2a7_clock_1, , , J1_ram_block2a7_clock_enable_1);
J1_ram_block2a7_PORT_A_write_enable = K1L1;
J1_ram_block2a7_PORT_A_write_enable_reg = DFFE(J1_ram_block2a7_PORT_A_write_enable, J1_ram_block2a7_clock_0, , , );
J1_ram_block2a7_PORT_B_read_enable = VCC;
J1_ram_block2a7_PORT_B_read_enable_reg = DFFE(J1_ram_block2a7_PORT_B_read_enable, J1_ram_block2a7_clock_1, , , J1_ram_block2a7_clock_enable_1);
J1_ram_block2a7_clock_0 = GLOBAL(clock);
J1_ram_block2a7_clock_1 = GLOBAL(clock);
J1_ram_block2a7_clock_enable_1 = D1_valid_rreq;
J1_ram_block2a7_PORT_B_data_out = MEMORY(J1_ram_block2a7_PORT_A_data_in_reg, , J1_ram_block2a7_PORT_A_address_reg, J1_ram_block2a7_PORT_B_address_reg, J1_ram_block2a7_PORT_A_write_enable_reg, J1_ram_block2a7_PORT_B_read_enable_reg, , , J1_ram_block2a7_clock_0, J1_ram_block2a7_clock_1, , J1_ram_block2a7_clock_enable_1, , );
J1_ram_block2a7 = J1_ram_block2a7_PORT_B_data_out[0];


--J1_ram_block2a8 is scfifo:scfifo_component|scfifo_39m:auto_generated|a_dpfifo_ihi:dpfifo|dpram_btj:FIFOram|altsyncram_9kb1:altsyncram1|ram_block2a8 at M4K_X15_Y21