?? altsyncram_9kb1.tdf
字號:
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a9 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a10 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a11 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a12 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a13 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a14 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block2a15 : stratix_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
address_a_wire[12..0] : WIRE;
address_b_wire[12..0] : WIRE;
BEGIN
address_reg_b[].CLK = clock1;
address_reg_b[].D = address_b[12..12];
address_reg_b[].ENA = clocken1;
decode3.data[0..0] = address_a_wire[12..12];
decode3.enable = wren_a;
mux4.data[] = ( ram_block2a[15].portbdataout[0..0], ram_block2a[14].portbdataout[0..0], ram_block2a[13].portbdataout[0..0], ram_block2a[12].portbdataout[0..0], ram_block2a[11].portbdataout[0..0], ram_block2a[10].portbdataout[0..0], ram_block2a[9].portbdataout[0..0], ram_block2a[8].portbdataout[0..0], ram_block2a[7].portbdataout[0..0], ram_block2a[6].portbdataout[0..0], ram_block2a[5].portbdataout[0..0], ram_block2a[4].portbdataout[0..0], ram_block2a[3].portbdataout[0..0], ram_block2a[2].portbdataout[0..0], ram_block2a[1].portbdataout[0..0], ram_block2a[0].portbdataout[0..0]);
mux4.sel[] = address_reg_b[].Q;
ram_block2a[15..0].clk0 = clock0;
ram_block2a[15..0].clk1 = clock1;
ram_block2a[15..0].ena1 = clocken1;
ram_block2a[0].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[1].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[2].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[3].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[4].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[5].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[6].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[7].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[8].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[9].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[10].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[11].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[12].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[13].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[14].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[15].portaaddr[] = ( B"0000", address_a_wire[11..0]);
ram_block2a[0].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
ram_block2a[1].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
ram_block2a[2].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
ram_block2a[3].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
ram_block2a[4].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
ram_block2a[5].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
ram_block2a[6].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
ram_block2a[7].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
ram_block2a[8].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
ram_block2a[9].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
ram_block2a[10].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
ram_block2a[11].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
ram_block2a[12].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
ram_block2a[13].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
ram_block2a[14].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
ram_block2a[15].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
ram_block2a[0].portawe = decode3.eq[0..0];
ram_block2a[1].portawe = decode3.eq[0..0];
ram_block2a[2].portawe = decode3.eq[0..0];
ram_block2a[3].portawe = decode3.eq[0..0];
ram_block2a[4].portawe = decode3.eq[0..0];
ram_block2a[5].portawe = decode3.eq[0..0];
ram_block2a[6].portawe = decode3.eq[0..0];
ram_block2a[7].portawe = decode3.eq[0..0];
ram_block2a[8].portawe = decode3.eq[1..1];
ram_block2a[9].portawe = decode3.eq[1..1];
ram_block2a[10].portawe = decode3.eq[1..1];
ram_block2a[11].portawe = decode3.eq[1..1];
ram_block2a[12].portawe = decode3.eq[1..1];
ram_block2a[13].portawe = decode3.eq[1..1];
ram_block2a[14].portawe = decode3.eq[1..1];
ram_block2a[15].portawe = decode3.eq[1..1];
ram_block2a[0].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[1].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[2].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[3].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[4].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[5].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[6].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[7].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[8].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[9].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[10].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[11].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[12].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[13].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[14].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[15].portbaddr[] = ( B"0000", address_b_wire[11..0]);
ram_block2a[0].portbrewe = B"1";
ram_block2a[1].portbrewe = B"1";
ram_block2a[2].portbrewe = B"1";
ram_block2a[3].portbrewe = B"1";
ram_block2a[4].portbrewe = B"1";
ram_block2a[5].portbrewe = B"1";
ram_block2a[6].portbrewe = B"1";
ram_block2a[7].portbrewe = B"1";
ram_block2a[8].portbrewe = B"1";
ram_block2a[9].portbrewe = B"1";
ram_block2a[10].portbrewe = B"1";
ram_block2a[11].portbrewe = B"1";
ram_block2a[12].portbrewe = B"1";
ram_block2a[13].portbrewe = B"1";
ram_block2a[14].portbrewe = B"1";
ram_block2a[15].portbrewe = B"1";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = mux4.result[];
END;
--VALID FILE
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