$ Start of Compile
#Wed Dec 22 23:53:44 2004

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"D:\prj_D\example-s1-1\FHT_example\after_optimized\wch_fht.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module wch_fht
Synthesizing module wch_fht
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Altera Technology Mapper, version 7.3.5, Build 250R, built Mar 18 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved



Writing Analyst data base D:\prj_D\example-s1-1\FHT_example\after_optimized\rev_2\wch_fht.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to D:\prj_D\example-s1-1\FHT_example\after_optimized\rev_2\wch_fht.xrf
Found clock wch_fht|Clk with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Dec 22 23:53:47 2004
#


Top view:               wch_fht
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 994.975

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
wch_fht|Clk        1.0 MHz       199.0 MHz     1000.000      5.025         994.975     inferred     Inferred_clkgroup_0
=======================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------
wch_fht|Clk  wch_fht|Clk  |  1000.000    994.975  |  No paths    -      |  No paths    -      |  No paths    -    
==================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: wch_fht|Clk
====================================



Starting Points with Worst Slack
********************************

                Starting                                                        Arrival            
Instance        Reference       Type                 Pin        Net             Time        Slack  
                Clock                                                                              
---------------------------------------------------------------------------------------------------
Cnt3_i_0[2]     wch_fht|Clk     cyclone_lcell_ff     regout     Cnt3_i_0[2]     0.173       994.975
Cnt3_i_0[0]     wch_fht|Clk     cyclone_lcell_ff     regout     Cnt3_i_0[0]     0.173       996.095
Cnt3_i_0[1]     wch_fht|Clk     cyclone_lcell_ff     regout     Cnt3_i_0[1]     0.173       996.209
FhtEn           wch_fht|Clk     cyclone_lcell_ff     regout     FhtEn           0.173       996.324
Out0[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out0[0]         0.173       996.770
Out1[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out1[0]         0.173       996.770
Out2[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out2[0]         0.173       996.770
Out3[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out3[0]         0.173       996.770
Out4[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out4[0]         0.173       996.770
Out5[0]         wch_fht|Clk     cyclone_lcell_ff     regout     Out5[0]         0.173       996.770
===================================================================================================


Ending Points with Worst Slack
******************************

             Starting                                                Required            
Instance     Reference       Type                 Pin     Net        Time         Slack  
             Clock                                                                       
-----------------------------------------------------------------------------------------
Out0[0]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[1]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[2]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[3]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[4]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[5]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[6]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[7]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[8]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
Out0[9]      wch_fht|Clk     cyclone_lcell_ff     ena     Out913     999.304      994.975
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    - Setup time:                            0.696
    = Required time:                         999.304

    - Propagation time:                      4.329
    = Slack (critical) :                     994.975

    Number of logic level(s):                1
    Starting point:                          Cnt3_i_0[2] / regout
    Ending point:                            Out0[0] / ena
    The start point is clocked by            wch_fht|Clk [rising] on pin clk
    The end   point is clocked by            wch_fht|Clk [rising] on pin clk

Instance / Net                          Pin         Pin               Arrival     No. of    
Name               Type                 Name        Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
Cnt3_i_0[2]        cyclone_lcell_ff     regout      Out     0.173     0.173       -         
Cnt3_i_0[2]        Net                  -           -       2.034     -           260       
Out913             cyclone_lcell        datad       In      -         2.207       -         
Out913             cyclone_lcell        combout     Out     0.088     2.295       -         
Out913             Net                  -           -       2.034     -           256       
Out0[0]            cyclone_lcell_ff     ena         In      -         4.329       -         
============================================================================================
Total path delay (propagation time + setup) of 5.025 is 0.957(19.0%) logic and 4.068(81.0%) route.



##### END OF TIMING REPORT #####]


##### START OF AREA REPORT #####[
Design view:work.wch_fht(verilog)
Selecting part EP1C3T100C6
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

I/O ATOMs:       0

Total LUTs:  518 of 2910 (17%)
Logic resources:  518 ATOMs of 2910 (17%)
ATOM count by mode:
  normal:       278
  arithmetic:   240

M4Ks:           0  (0% of 13)
Total ESB:      0 bits 

ATOMs using regout pin: 260
  also using enable pin: 257
  also using combout pin: 0
ATOMs using combout pin: 258
Number of Inputs on ATOMs: 2317
Number of Nets:   955

##### END OF AREA REPORT #####]

Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
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