{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version " "Info: Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 13 22:26:53 2004 " "Info: Processing started: Mon Sep 13 22:26:53 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Diff_io_top -c Diff_io_top " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Diff_io_top -c Diff_io_top" {  } {  } 0}
{ "Info" "ISGN_AE_SOURCE_FILE_IS" "sld_hub.vhd " "Info: Used source file sld_hub.vhd for a SignalTap II or debug node instance" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/examples/Examples-10-2/Verilog/sld_hub.vhd " "Warning: Can't analyze file -- file E:/examples/Examples-10-2/Verilog/sld_hub.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "Diff_io_top.v 1 1 " "Info: Using design file Diff_io_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Diff_io_top " "Info: Found entity 1: Diff_io_top" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "Diff_io_top" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lvds_rx.v 1 1 " "Info: Using design file lvds_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lvds_rx " "Info: Found entity 1: lvds_rx" {  } { { "E:/examples/Examples-10-2/Verilog/lvds_rx.v" "lvds_rx" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_rx.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altlvds_rx " "Info: Found entity 1: altlvds_rx" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "altlvds_rx" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 170 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mult.v 1 1 " "Info: Using design file mult.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mult " "Info: Found entity 1: mult" {  } { { "E:/examples/Examples-10-2/Verilog/mult.v" "mult" "" { Text "E:/examples/Examples-10-2/Verilog/mult.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altmult_add " "Info: Found entity 1: altmult_add" {  } { { "d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf" "altmult_add" "" { Text "d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf" 300 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_v4n1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_v4n1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_v4n1 " "Info: Found entity 1: mult_add_v4n1" {  } { { "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" "mult_add_v4n1" "" { Text "E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lvds_tx.v 1 1 " "Info: Using design file lvds_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lvds_tx " "Info: Found entity 1: lvds_tx" {  } { { "E:/examples/Examples-10-2/Verilog/lvds_tx.v" "lvds_tx" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_tx.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altlvds_tx " "Info: Found entity 1: altlvds_tx" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "altlvds_tx" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 216 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "32 " "Info: Implemented 32 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "2 " "Info: Implemented 2 ClockLock PLLs" {  } {  } 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "1 " "Info: Implemented 1 DSP elements" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 13 22:26:55 2004 " "Info: Processing ended: Mon Sep 13 22:26:55 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}