{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version " "Info: Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 13 22:26:57 2004 " "Info: Processing started: Mon Sep 13 22:26:57 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off Diff_io_top -c Diff_io_top " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off Diff_io_top -c Diff_io_top" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Diff_io_top EP1S10F780C6 " "Info: Selected device EP1S10F780C6 for design Diff_io_top" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll " "Info: Implementing parameter values for PLL lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll 8 1 0 0 " "Info: Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll port" {  } {  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock port" {  } {  } 0}  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 402 7 0 } } { "E:/examples/Examples-10-2/Verilog/lvds_rx.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_rx.v" 64 -1 0 } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 37 -1 0 } }  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll " "Info: Implementing parameter values for PLL lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll 8 1 0 0 " "Info: Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll port" {  } {  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll~CLK1 8 1 0 0 " "Info: Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll~CLK1 port" {  } {  } 0}  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 397 5 0 } } { "E:/examples/Examples-10-2/Verilog/lvds_tx.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_tx.v" 58 -1 0 } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 55 -1 0 } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_FAST_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Fast Fit compilation -- Fitter effort will be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F780I6 " "Info: Device EP1S10F780I6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F780C6ES " "Info: Device EP1S10F780C6ES is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F780C6 " "Info: Device EP1S20F780C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F780I6 " "Info: Device EP1S20F780I6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F780C6 " "Info: Device EP1S25F780C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F780I6 " "Info: Device EP1S25F780I6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S30F780C6 " "Info: Device EP1S30F780C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S30F780I6 " "Info: Device EP1S30F780I6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S30F780C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S30F780C6_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S40F780C6 " "Info: Device EP1S40F780C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S40F780C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S40F780C6_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RESERVE_PIN_NO_DATA0" "" "Info: DATA\[0\] dual-purpose pin not reserved" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "LVDS Placement Operation Initializations " "Info: Completed LVDS Placement Operation Initializations" {  } {  } 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "8 8 " "Info: No exact pin location assignment(s) for 8 pins of 8 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rx_locked " "Info: Pin rx_locked not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rx_locked" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { rx_locked } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { rx_locked } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "tx_out\[1\] " "Info: Pin tx_out\[1\] not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 24 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tx_out\[1\]" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { tx_out[1] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { tx_out[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "tx_out\[0\] " "Info: Pin tx_out\[0\] not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 24 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tx_out\[0\]" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { tx_out[0] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { tx_out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "tx_outclock " "Info: Pin tx_outclock not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tx_outclock" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { tx_outclock } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { tx_outclock } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rx_data_align " "Info: Pin rx_data_align not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 23 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rx_data_align" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { rx_data_align } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { rx_data_align } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rx_inclock " "Info: Pin rx_inclock not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 22 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rx_inclock" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { rx_inclock } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { rx_inclock } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rx_in\[0\] " "Info: Pin rx_in\[0\] not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 21 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rx_in\[0\]" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { rx_in[0] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { rx_in[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rx_in\[1\] " "Info: Pin rx_in\[1\] not assigned to an exact location on the device" {  } { { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 21 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rx_in\[1\]" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { rx_in[1] } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { rx_in[1] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll " "Info: Implementing parameter values for PLL lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll 8 1 0 0 " "Info: Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll port" {  } {  } 0}  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf" 397 5 0 } } { "E:/examples/Examples-10-2/Verilog/lvds_tx.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_tx.v" 58 -1 0 } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 55 -1 0 } }  } 0}
{ "Warning" "WFYGR_FYGR_NO_BYTE_ENABLE_SYNCH_REG" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll " "Warning: For fast PLL lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll comparator input port is not synchronized to the core clock" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 402 7 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll } "NODE_NAME" } }  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll " "Info: Implementing parameter values for PLL lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll 8 1 0 0 " "Info: Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll port" {  } {  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|rx_outclock port" {  } {  } 0}  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 402 7 0 } } { "E:/examples/Examples-10-2/Verilog/lvds_rx.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/lvds_rx.v" 64 -1 0 } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" "" "" { Text "E:/examples/Examples-10-2/Verilog/Diff_io_top.v" 37 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Regular LVDS Placement Operation " "Info: Completed Regular LVDS Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_HSDI_PLLS_MERGED" "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll " "Info: Receiver fast PLL lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll and transmitter fast PLL lvds_tx:lvds_tx_inst\|altlvds_tx:altlvds_tx_component\|pll are merged together" {  } { { "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf" 402 7 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "lvds_rx:lvds_rx_inst\|altlvds_rx:altlvds_rx_component\|pll" } } } } { "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" "" "" { Report "E:/examples/Examples-10-2/Verilog/db/Diff_io_top_cmp.qrpt" Compiler "Diff_io_top" "UNKNOWN" "V1" "E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db" { Floorplan "" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll } "NODE_NAME" } } } { "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { Floorplan "E:/examples/Examples-10-2/Verilog/Diff_io_top.fld" "" "" { lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Flexible LVDS Placement Operation " "Info: Completed Flexible LVDS Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}