Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version
34
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# entity
Diff_io_top
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Diff_io_top.v
1095085333
7
# storage
db|Diff_io_top.(0).cnf
db|Diff_io_top.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
lvds_rx
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lvds_rx.v
1095085321
7
# storage
db|Diff_io_top.(1).cnf
db|Diff_io_top.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altlvds_rx
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altlvds_rx.tdf
1088009416
6
# storage
db|Diff_io_top.(2).cnf
db|Diff_io_top.(2).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
NUMBER_OF_CHANNELS
2
PARAMETER_DEC
USR
DESERIALIZATION_FACTOR
8
PARAMETER_DEC
USR
REGISTERED_OUTPUT
ON
PARAMETER_UNKNOWN
USR
INCLOCK_PERIOD
9523
PARAMETER_DEC
USR
INCLOCK_BOOST
8
PARAMETER_UNKNOWN
DEF
CDS_MODE
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
INPUT_DATA_RATE
840
PARAMETER_DEC
USR
INCLOCK_DATA_ALIGNMENT
EDGE_ALIGNED
PARAMETER_UNKNOWN
USR
REGISTERED_DATA_ALIGN_INPUT
OFF
PARAMETER_UNKNOWN
USR
COMMON_RX_TX_PLL
ON
PARAMETER_UNKNOWN
USR
ENABLE_DPA_MODE
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_DPA_FIFO
ON
PARAMETER_UNKNOWN
DEF
USE_DPLL_RAWPERROR
OFF
PARAMETER_UNKNOWN
DEF
USE_CORECLOCK_INPUT
OFF
PARAMETER_UNKNOWN
DEF
DPLL_LOCK_COUNT
0
PARAMETER_UNKNOWN
DEF
DPLL_LOCK_WINDOW
0
PARAMETER_UNKNOWN
DEF
OUTCLOCK_RESOURCE
AUTO
PARAMETER_UNKNOWN
USR
DATA_ALIGN_ROLLOVER
8
PARAMETER_UNKNOWN
DEF
LOSE_LOCK_ON_ONE_CHANGE
OFF
PARAMETER_UNKNOWN
DEF
RESET_FIFO_AT_FIRST_LOCK
ON
PARAMETER_UNKNOWN
DEF
USE_EXTERNAL_PLL
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
rx_data_align
rx_in
rx_in
rx_inclock
rx_locked
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_out
rx_outclock
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|apex20ke_lvds_receiver.inc
1081477760
d:|altera|quartus41|libraries|megafunctions|apex20ke_pll.inc
1081477770
d:|altera|quartus41|libraries|megafunctions|mercury_hssi_receiver.inc
1081479006
d:|altera|quartus41|libraries|megafunctions|mercury_hssi_pll.inc
1081479000
d:|altera|quartus41|libraries|megafunctions|apexii_hsdi_receiver.inc
1081477846
d:|altera|quartus41|libraries|megafunctions|apexii_pll.inc
1081477866
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
d:|altera|quartus41|libraries|megafunctions|stratix_lvds_receiver.inc
1081479442
d:|altera|quartus41|libraries|megafunctions|stratix_pll.inc
1081479492
d:|altera|quartus41|libraries|megafunctions|stratixgx_lvds_receiver.inc
1081479528
d:|altera|quartus41|libraries|megafunctions|stratixgx_pll.inc
1081479540
d:|altera|quartus41|libraries|megafunctions|stratixii_lvds_receiver.inc
1081479732
d:|altera|quartus41|libraries|megafunctions|stratixii_clkctrl.inc
1088018008
d:|altera|quartus41|libraries|megafunctions|altddio_in.inc
1081477280
}
# end
# entity
mult
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mult.v
1013161302
7
# storage
db|Diff_io_top.(3).cnf
db|Diff_io_top.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altmult_add
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altmult_add.tdf
1088009420
6
# storage
db|Diff_io_top.(4).cnf
db|Diff_io_top.(4).cnf
# user_parameter {
NUMBER_OF_MULTIPLIERS
1
PARAMETER_DEC
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTH_B
8
PARAMETER_DEC
USR
WIDTH_RESULT
16
PARAMETER_DEC
USR
INPUT_REGISTER_A0
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
REPRESENTATION_A
UNUSED
PARAMETER_UNKNOWN
DEF
SIGNED_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B0
CLOCK0
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
REPRESENTATION_B
UNUSED
PARAMETER_UNKNOWN
DEF
SIGNED_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR0
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
UNUSED
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
DEF
DSP_BLOCK_BALANCING
Auto
DSP_BLOCK_BALANCING_IMPLEMENTATION
USR
CBXI_PARAMETER
mult_add_v4n1
PARAMETER_UNKNOWN
USR
}
# used_port {
clock0
dataa
dataa
dataa
dataa
dataa
dataa
dataa
dataa
datab
datab
datab
datab
datab
datab
datab
datab
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|stratix_mac_mult.inc
1081479466
d:|altera|quartus41|libraries|megafunctions|stratix_mac_out.inc
1081479484
}
# end
# entity
mult_add_v4n1
# case_insensitive
# source_file
db|mult_add_v4n1.tdf
1095085375
6
# storage
db|Diff_io_top.(5).cnf
db|Diff_io_top.(5).cnf
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
clock0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# end
# entity
lvds_tx
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lvds_tx.v
1095085253
7
# storage
db|Diff_io_top.(6).cnf
db|Diff_io_top.(6).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altlvds_tx
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altlvds_tx.tdf
1088009416
6
# storage
db|Diff_io_top.(7).cnf
db|Diff_io_top.(7).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
NUMBER_OF_CHANNELS
2
PARAMETER_DEC
USR
DESERIALIZATION_FACTOR
8
PARAMETER_DEC
USR
REGISTERED_INPUT
TX_CLKIN
PARAMETER_UNKNOWN
USR
MULTI_CLOCK
OFF
PARAMETER_UNKNOWN
DEF
INCLOCK_PERIOD
9523
PARAMETER_DEC
USR
OUTCLOCK_DIVIDE_BY
8
PARAMETER_DEC
USR
INCLOCK_BOOST
0
PARAMETER_UNKNOWN
DEF
CENTER_ALIGN_MSB
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OUTPUT_DATA_RATE
840
PARAMETER_DEC
USR
INCLOCK_DATA_ALIGNMENT
EDGE_ALIGNED
PARAMETER_UNKNOWN
USR
OUTCLOCK_ALIGNMENT
EDGE_ALIGNED
PARAMETER_UNKNOWN
USR
COMMON_RX_TX_PLL
ON
PARAMETER_UNKNOWN
USR
OUTCLOCK_RESOURCE
AUTO
PARAMETER_UNKNOWN
USR
USE_EXTERNAL_PLL
OFF
PARAMETER_UNKNOWN
DEF
PREEMPHASIS_SETTING
0
PARAMETER_UNKNOWN
DEF
VOD_SETTING
0
PARAMETER_UNKNOWN
DEF
DIFFERENTIAL_DRIVE
0
PARAMETER_UNKNOWN
DEF
}
# used_port {
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_in
tx_inclock
tx_out
tx_out
tx_outclock
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|apex20ke_lvds_transmitter.inc
1081477764
d:|altera|quartus41|libraries|megafunctions|apex20ke_pll.inc
1081477770
d:|altera|quartus41|libraries|megafunctions|mercury_hssi_transmitter.inc
1081479018
d:|altera|quartus41|libraries|megafunctions|mercury_hssi_pll.inc
1081479000
d:|altera|quartus41|libraries|megafunctions|apexii_hsdi_transmitter.inc
1081477852
d:|altera|quartus41|libraries|megafunctions|apexii_pll.inc
1081477866
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
d:|altera|quartus41|libraries|megafunctions|stratix_pll.inc
1081479492
d:|altera|quartus41|libraries|megafunctions|stratix_lvds_transmitter.inc
1081479454
d:|altera|quartus41|libraries|megafunctions|stratixii_lvds_transmitter.inc
1081479740
d:|altera|quartus41|libraries|megafunctions|stratixgx_lvds_transmitter.inc
1081479534
d:|altera|quartus41|libraries|megafunctions|stratixgx_pll.inc
1081479540
d:|altera|quartus41|libraries|megafunctions|stratixii_clkctrl.inc
1088018008
d:|altera|quartus41|libraries|megafunctions|altddio_out.inc
1081477304
}
# end
# complete