?? fsk.map.rpt
字號:
Analysis & Synthesis report for FSK
Sun May 06 21:27:08 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. Analysis & Synthesis DSP Block Usage Summary
9. Registers Removed During Synthesis
10. General Register Statistics
11. Source assignments for dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_26u:auto_generated
12. Parameter Settings for User Entity Instance: sMuxAltr:nto1Multiplexeri
13. Parameter Settings for User Entity Instance: sMuxAltr:nto1Multiplexeri|LPM_MUX:\gc:U0
14. Parameter Settings for User Entity Instance: dds:ddsi|SBF:AltBusi
15. Parameter Settings for User Entity Instance: dds:ddsi|SBF:AltBusi|sAltrPropagate:u0
16. Parameter Settings for User Entity Instance: dds:ddsi|SDelay:Delayi
17. Parameter Settings for User Entity Instance: dds:ddsi|SDelay:Delayi|sAltrPropagate:u0
18. Parameter Settings for User Entity Instance: dds:ddsi|AltiMult:Producti
19. Parameter Settings for User Entity Instance: dds:ddsi|SAdderSub:ParallelAdderSubtractori
20. Parameter Settings for User Entity Instance: dds:ddsi|SAdderSub:ParallelAdderSubtractori|LPM_ADD_SUB:\pip:genaa:U0
21. Parameter Settings for User Entity Instance: dds:ddsi|SAdderSub:ParallelAdderSubtractor1i
22. Parameter Settings for User Entity Instance: dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|LPM_ADD_SUB:\pip:genaa:U0
23. Parameter Settings for User Entity Instance: dds:ddsi|SRED:BusConversioni
24. Parameter Settings for User Entity Instance: dds:ddsi|SRED:BusConversion1i
25. Parameter Settings for Inferred Entity Instance: dds:ddsi|altsyncram:Mux0_rtl_0
26. Parameter Settings for Inferred Entity Instance: dds:ddsi|AltiMult:Producti|lpm_mult:Mult0
27. lpm_mult Parameter Settings by Entity Instance
28. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun May 06 21:27:08 2007 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; FSK ;
; Top-level Entity Name ; FSK ;
; Family ; Stratix ;
; Total logic elements ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name ; FSK ; FSK ;
; Family name ; stratix ; Stratix ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
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