+-------+--------------+------------+------+--------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 7.689 ns   ; q_temp ; q  ; cp         ;
+-------+--------------+------------+--------+----+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -4.330 ns ; t    ; q_temp ; cp       ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 21:18:09 2007
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off T -c T --speed=8
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
    Info: Pin "q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" Internal fmax is restricted to 360.1 MHz between source register "q_temp" and destination register "q_temp"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.501 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
            Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
            Info: Total cell delay = 0.501 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cp" to destination register is 2.949 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
                Info: Total cell delay = 1.600 ns ( 54.26 % )
                Info: Total interconnect delay = 1.349 ns ( 45.74 % )
            Info: - Longest clock path from clock "cp" to source register is 2.949 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
                Info: Total cell delay = 1.600 ns ( 54.26 % )
                Info: Total interconnect delay = 1.349 ns ( 45.74 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q_temp" (data pin = "t", clock pin = "cp") is 4.596 ns
    Info: + Longest pin to register delay is 7.585 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 't'
        Info: 2: + IC(6.327 ns) + CELL(0.206 ns) = 7.477 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.585 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: Total cell delay = 1.258 ns ( 16.59 % )
        Info: Total interconnect delay = 6.327 ns ( 83.41 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.949 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: Total cell delay = 1.600 ns ( 54.26 % )
        Info: Total interconnect delay = 1.349 ns ( 45.74 % )
Info: tco from clock "cp" to destination pin "q" through register "q_temp" is 7.689 ns
    Info: + Longest clock path from clock "cp" to source register is 2.949 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: Total cell delay = 1.600 ns ( 54.26 % )
        Info: Total interconnect delay = 1.349 ns ( 45.74 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.436 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: 2: + IC(1.390 ns) + CELL(3.046 ns) = 4.436 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 3.046 ns ( 68.67 % )
        Info: Total interconnect delay = 1.390 ns ( 31.33 % )
Info: th for register "q_temp" (data pin = "t", clock pin = "cp") is -4.330 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.949 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: Total cell delay = 1.600 ns ( 54.26 % )
        Info: Total interconnect delay = 1.349 ns ( 45.74 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.585 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 't'
        Info: 2: + IC(6.327 ns) + CELL(0.206 ns) = 7.477 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.585 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'
        Info: Total cell delay = 1.258 ns ( 16.59 % )
        Info: Total interconnect delay = 6.327 ns ( 83.41 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Sun May 27 21:18:12 2007
    Info: Elapsed time: 00:00:03