?? cpld_dsp.rpt
字號:
|lpm_add_sub:1458|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1458|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1459|
|lpm_add_sub:1459|addcore:adder|
|lpm_add_sub:1459|addcore:adder|addcore:adder1|
|lpm_add_sub:1459|addcore:adder|addcore:adder0|
|lpm_add_sub:1459|altshift:result_ext_latency_ffs|
|lpm_add_sub:1459|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1459|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1460|
|lpm_add_sub:1460|addcore:adder|
|lpm_add_sub:1460|addcore:adder|addcore:adder1|
|lpm_add_sub:1460|addcore:adder|addcore:adder0|
|lpm_add_sub:1460|altshift:result_ext_latency_ffs|
|lpm_add_sub:1460|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1460|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1461|
|lpm_add_sub:1461|addcore:adder|
|lpm_add_sub:1461|altshift:result_ext_latency_ffs|
|lpm_add_sub:1461|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1461|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1462|
|lpm_add_sub:1462|addcore:adder|
|lpm_add_sub:1462|altshift:result_ext_latency_ffs|
|lpm_add_sub:1462|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1462|altshift:oflow_ext_latency_ffs|
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
***** Logic for device 'cpld_dsp' compiled without errors.
Device: EPM7128SQC100-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R
E
V S d
C G G V E p
E E E C C C C R _
O R C G A A A I L G G L G E E E C E V n
E W E N 1 1 1 N K N N K N A A A I A E u
1 1 1 D 2 1 0 T 2 D D 1 D 9 8 7 O 6 D m
------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 |_
/ 99 97 95 93 91 89 87 85 83 81 |
ED11 | 1 80 | EA5
ED10 | 2 79 | RESERVED
ED9 | 3 78 | RESERVED
ED8 | 4 77 | delaytime1
VCCIO | 5 76 | GND
#TDI | 6 75 | #TDO
ED7 | 7 74 | LED0
ED6 | 8 73 | RESERVED
ED5 | 9 72 | RESERVED
ED4 | 10 71 | EA4
ED3 | 11 70 | LED1
ED2 | 12 69 | KEY0
GND | 13 68 | VCCIO
ED1 | 14 67 | KEY1
ED0 | 15 66 | KEY2
EA0 | 16 EPM7128SQC100-6 65 | KEY3
#TMS | 17 64 | #TCK
EA1 | 18 63 | KEY4
EA2 | 19 62 | RESERVED
VCCIO | 20 61 | GND
wr_en1 | 21 60 | RESERVED
RESERVED | 22 59 | RESERVED
CE2 | 23 58 | ad_num0
RW2 | 24 57 | ad_num1
OE2 | 25 56 | RESERVED
AD2_RD | 26 55 | RESERVED
AD2_BUSY | 27 54 | EA3
GND | 28 53 | VCCIO
AD1_RD | 29 52 | RESERVED
AD1_BUSY | 30 51 | RESERVED
| 32 34 36 38 40 42 44 46 48 50 _|
\ 31 33 35 37 39 41 43 45 47 49 |
\-------------------------------------------
A A A A A V A A A G V A A A G A A A C R
D D D D D C D D D N C D D D N D D D O E
9 1 1 8 7 C 6 5 4 D C 3 2 1 D 0 3 3 N S
0 1 I I _ _ V E
O N R B R
T D U V
S E
Y D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 10/10(100%) 7/16( 43%) 27/36( 75%)
B: LC17 - LC32 11/16( 68%) 10/10(100%) 8/16( 50%) 22/36( 61%)
C: LC33 - LC48 9/16( 56%) 9/10( 90%) 16/16(100%) 26/36( 72%)
D: LC49 - LC64 9/16( 56%) 10/10(100%) 4/16( 25%) 29/36( 80%)
E: LC65 - LC80 13/16( 81%) 7/10( 70%) 12/16( 75%) 32/36( 88%)
F: LC81 - LC96 14/16( 87%) 5/10( 50%) 14/16( 87%) 28/36( 77%)
G: LC97 - LC112 12/16( 75%) 8/10( 80%) 12/16( 75%) 32/36( 88%)
H: LC113 - LC128 7/16( 43%) 7/10( 70%) 11/16( 68%) 27/36( 75%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 66/80 ( 82%)
Total logic cells used: 82/128 ( 64%)
Total shareable expanders used: 52/128 ( 40%)
Total Turbo logic cells used: 82/128 ( 64%)
Total shareable expanders not available (n/a): 32/128 ( 25%)
Average fan-in: 8.31
Total fan-in: 682
Total input pins required: 37
Total fast input logic cells required: 0
Total output pins required: 27
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 82
Total flipflops required: 19
Total product terms required: 293
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 39
Logic cells inserted for fitting: 2
Synthesized logic cells: 19/ 128 ( 14%)
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
58 (88) (F) INPUT s 0 0 0 0 0 8 16 ad_num0
57 (86) (F) INPUT s 0 0 0 0 0 6 16 ad_num1
46 (70) (E) INPUT 0 0 0 0 0 1 0 AD0
30 (62) (D) INPUT 0 0 0 0 0 10 12 AD1_BUSY
44 (69) (E) INPUT 0 0 0 0 0 1 0 AD1
27 (33) (C) INPUT 0 0 0 0 0 0 0 AD2_BUSY
43 (67) (E) INPUT 0 0 0 0 0 1 0 AD2
48 (73) (E) INPUT 0 0 0 0 0 0 0 AD3_BUSY
42 (65) (E) INPUT 0 0 0 0 0 1 0 AD3
39 (49) (D) INPUT 0 0 0 0 0 1 0 AD4
38 (51) (D) INPUT 0 0 0 0 0 1 0 AD5
37 (53) (D) INPUT 0 0 0 0 0 1 0 AD6
35 (54) (D) INPUT 0 0 0 0 0 1 0 AD7
34 (56) (D) INPUT 0 0 0 0 0 1 0 AD8
31 (61) (D) INPUT 0 0 0 0 0 1 0 AD9
32 (59) (D) INPUT 0 0 0 0 0 1 0 AD10
33 (57) (D) INPUT 0 0 0 0 0 1 0 AD11
77 (113) (H) INPUT s 0 0 0 0 0 10 16 delaytime1
81 (120) (H) INPUT s 0 0 0 0 0 4 10 dp_num
16 (17) (B) INPUT s 0 0 0 0 0 10 22 EA0
18 (46) (C) INPUT s 0 0 0 0 0 10 22 EA1
19 (45) (C) INPUT s 0 0 0 0 0 10 23 EA2
83 (123) (H) INPUT s 0 0 0 0 0 8 11 EA6
85 (125) (H) INPUT s 0 0 0 0 0 8 9 EA7
86 (126) (H) INPUT s 0 0 0 0 0 8 11 EA8
87 (128) (H) INPUT s 0 0 0 0 0 8 9 EA9
94 (16) (A) INPUT s 0 0 0 0 0 8 12 EA10
95 (14) (A) INPUT s 0 0 0 0 0 0 1 EA11
96 (13) (A) INPUT s 0 0 0 0 0 0 1 EA12
89 - - INPUT G 0 0 0 0 0 0 0 GCLK1
92 - - INPUT G 0 0 0 0 0 0 0 GCLK2
69 (102) (G) INPUT 0 0 0 0 0 0 0 KEY0
67 (101) (G) INPUT 0 0 0 0 0 0 0 KEY1
66 (99) (G) INPUT 0 0 0 0 0 0 0 KEY2
65 (97) (G) INPUT 0 0 0 0 0 0 0 KEY3
63 (94) (F) INPUT 0 0 0 0 0 0 0 KEY4
21 (43) (C) INPUT s 0 0 0 0 0 10 0 wr_en1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
29 64 D FF + t 2 0 1 13 9 1 3 AD1_RD (:1200)
26 35 C FF + t 6 0 1 10 8 1 2 AD2_RD (:1257)
47 72 E FF + t 6 0 1 10 8 1 2 AD3_RD (:1431)
98 11 A FF + t 6 5 1 14 9 2 2 CE1 (:1137)
23 40 C FF + t 4 3 1 10 5 2 1 CE2 (:1136)
49 75 E FF + t 0 0 0 0 7 0 0 CONV (:1374)
54 81 F FF + t 9 6 1 12 11 9 25 EA3 (:984)
71 105 G FF + t 9 6 1 12 11 10 22 EA4 (:983)
80 118 H FF + t 9 5 1 13 10 8 14 EA5 (:982)
15 19 B OUTPUT t 0 0 0 1 0 0 0 ED0
14 21 B OUTPUT t 0 0 0 1 0 0 0 ED1
12 22 B OUTPUT t 0 0 0 1 0 0 0 ED2
11 24 B OUTPUT t 0 0 0 1 0 0 0 ED3
10 25 B OUTPUT t 0 0 0 1 0 0 0 ED4
9 27 B OUTPUT t 0 0 0 1 0 0 0 ED5
8 29 B OUTPUT t 0 0 0 1 0 0 0 ED6
7 30 B OUTPUT t 0 0 0 1 0 0 0 ED7
4 1 A OUTPUT t 0 0 0 1 0 0 0 ED8
3 3 A OUTPUT t 0 0 0 1 0 0 0 ED9
2 5 A OUTPUT t 0 0 0 1 0 0 0 ED10
1 6 A OUTPUT t 0 0 0 1 0 0 0 ED11
74 110 G OUTPUT t 0 0 0 0 0 0 0 LED0
70 104 G OUTPUT t 0 0 0 0 0 0 0 LED1
100 8 A OUTPUT t 0 0 0 0 0 0 0 OE1
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -