?? cpld_dsp.rpt
字號:
25 37 C OUTPUT t 0 0 0 0 0 0 0 OE2
99 9 A FF + t 6 5 1 14 9 0 0 RW1 (~1137~1)
24 38 C FF + t 4 3 1 10 6 1 0 RW2 (~1136~1)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(48) 73 E SOFT s t r 0 0 0 1 0 8 8 EA11
(44) 69 E SOFT s t r 0 0 0 1 0 10 7 EA12
(85) 125 H SOFT t 0 0 0 3 1 1 2 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node3
(55) 83 F SOFT t 0 0 0 3 2 1 2 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node4
- 95 F SOFT t 0 0 0 3 3 1 2 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node5
(82) 121 H SOFT t 0 0 0 3 1 0 2 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node3
(64) 96 F SOFT t 0 0 0 3 2 0 2 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node4
(63) 94 F SOFT t 0 0 0 3 3 0 2 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node5
(83) 123 H SOFT t 0 0 0 3 1 1 2 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node3
- 114 H SOFT t 0 0 0 3 2 1 2 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node4
- 92 F SOFT t 0 0 0 3 3 1 1 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node5
(31) 61 D SOFT t 0 0 0 3 1 1 2 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node3
- 63 D SOFT t 0 0 0 3 2 1 2 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node4
- 90 F SOFT t 0 0 0 3 3 1 2 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node5
- 60 D SOFT t 0 0 0 3 1 0 2 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node3
- 58 D SOFT t 0 0 0 3 2 0 2 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node4
- 87 F SOFT t 0 0 0 3 3 0 2 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node5
(33) 57 D SOFT t 0 0 0 3 1 1 2 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node3
(30) 62 D SOFT t 0 0 0 3 2 1 2 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node4
- 84 F SOFT t 0 0 0 3 3 1 2 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node5
- 66 E SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:1461|addcore:adder|result_node3
(73) 109 G SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:1461|addcore:adder|result_node4
- 111 G SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1461|addcore:adder|result_node5
(69) 102 G SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1461|addcore:adder|result_node6
(46) 70 E SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1461|addcore:adder|result_node7
- 100 G SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:1462|addcore:adder|result_node3
(67) 101 G SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:1462|addcore:adder|result_node4
(75) 112 G SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1462|addcore:adder|result_node5
(42) 65 E SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1462|addcore:adder|result_node6
- 68 E SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1462|addcore:adder|result_node7
- 116 H SOFT s t 1 0 1 8 8 1 0 ~968~1
(77) 113 H SOFT s t 1 0 1 5 7 1 0 ~968~2
(32) 59 D SOFT s t 1 0 1 5 6 1 0 ~969~1
- 55 D SOFT s t 1 0 1 5 7 1 0 ~969~2
- 82 F SOFT s t 1 0 1 5 6 1 0 ~970~1
(58) 88 F SOFT s t 1 0 1 5 7 1 0 ~970~2
- 36 C SOFT s t 1 0 1 8 3 2 0 ~1133~1
(59) 89 F SOFT s t 1 0 1 11 5 2 0 ~1134~1
(60) 91 F SOFT s t 1 0 1 12 5 2 0 ~1134~2
(62) 93 F SOFT s t 1 0 1 9 4 2 0 ~1134~3
(65) 97 G SOFT s t 1 0 1 12 4 1 0 ~1198~1
- 98 G SOFT s t 1 0 1 7 4 1 0 ~1198~2
- 103 G SOFT s t 1 0 1 5 3 1 0 ~1198~3
(19) 45 C SOFT s t 1 0 1 12 4 1 0 ~1255~1
(18) 46 C SOFT s t 1 0 1 7 4 1 0 ~1255~2
(6) 32 B DFFE + t 4 2 1 0 10 1 9 num_add7 (:1360)
(16) 17 B DFFE + t 4 2 1 0 10 1 11 num_add6 (:1361)
(51) 78 E DFFE + t 4 2 1 0 10 1 13 num_add5 (:1362)
- 71 E DFFE + t 4 2 1 0 10 1 15 num_add4 (:1363)
- 28 B DFFE + t 4 2 1 0 10 1 17 num_add3 (:1364)
- 74 E TFFE + t 0 0 0 0 8 1 17 num_add2 (:1365)
- 76 E TFFE + t 0 0 0 0 1 1 17 num_add1 (:1366)
(50) 77 E TFFE + t 0 0 0 0 8 0 18 num_add0 (:1367)
- 47 C SOFT s t 1 0 1 12 4 1 0 ~1429~1
- 34 C SOFT s t 1 0 1 7 4 1 0 ~1429~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC11 CE1
| +----------- LC1 ED8
| | +--------- LC3 ED9
| | | +------- LC5 ED10
| | | | +----- LC6 ED11
| | | | | +--- LC8 OE1
| | | | | | +- LC9 RW1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC11 -> * - - - - - * | * - - - - * - - | <-- CE1
Pin
58 -> * - - - - - * | * - * * * * * * | <-- ad_num0
57 -> * - - - - - * | * - * * * * * * | <-- ad_num1
30 -> * - - - - - * | * - * * * * * * | <-- AD1_BUSY
34 -> - * - - - - - | * - - - - - - - | <-- AD8
31 -> - - * - - - - | * - - - - - - - | <-- AD9
32 -> - - - * - - - | * - - - - - - - | <-- AD10
33 -> - - - - * - - | * - - - - - - - | <-- AD11
77 -> * - - - - - * | * - * * * * * * | <-- delaytime1
81 -> * - - - - - * | * - * * - * - * | <-- dp_num
16 -> * - - - - - * | * - * * * * * * | <-- EA0
18 -> * - - - - - * | * - * * * * * * | <-- EA1
19 -> * - - - - - * | * - * * * * * * | <-- EA2
83 -> * - - - - - * | * - * * - * * * | <-- EA6
85 -> * - - - - - * | * - * * * * * * | <-- EA7
86 -> * - - - - - * | * - * * - * * * | <-- EA8
87 -> * - - - - - * | * - * * * * * * | <-- EA9
94 -> * - - - - - * | * - * * - * * * | <-- EA10
89 -> - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - * | * - * * * * * * | <-- wr_en1
LC81 -> * - - - - - * | * - * * * * * * | <-- EA3
LC105-> * - - - - - * | * - * * * * * * | <-- EA4
LC118-> * - - - - - * | * - * * * * * * | <-- EA5
LC73 -> * - - - - - * | * - * * * * * * | <-- EA11
LC69 -> * - - - - - * | * - * * * * * * | <-- EA12
LC89 -> * - - - - - * | * - - - - - - - | <-- ~1134~1
LC91 -> * - - - - - * | * - - - - - - - | <-- ~1134~2
LC93 -> * - - - - - * | * - - - - - - - | <-- ~1134~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC19 ED0
| +------------------- LC21 ED1
| | +----------------- LC22 ED2
| | | +--------------- LC24 ED3
| | | | +------------- LC25 ED4
| | | | | +----------- LC27 ED5
| | | | | | +--------- LC29 ED6
| | | | | | | +------- LC30 ED7
| | | | | | | | +----- LC32 num_add7
| | | | | | | | | +--- LC17 num_add6
| | | | | | | | | | +- LC28 num_add3
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC32 -> - - - - - - - - * * * | - * - - * - - - | <-- num_add7
LC17 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add6
LC28 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add3
Pin
46 -> * - - - - - - - - - - | - * - - - - - - | <-- AD0
44 -> - * - - - - - - - - - | - * - - - - - - | <-- AD1
43 -> - - * - - - - - - - - | - * - - - - - - | <-- AD2
42 -> - - - * - - - - - - - | - * - - - - - - | <-- AD3
39 -> - - - - * - - - - - - | - * - - - - - - | <-- AD4
38 -> - - - - - * - - - - - | - * - - - - - - | <-- AD5
37 -> - - - - - - * - - - - | - * - - - - - - | <-- AD6
35 -> - - - - - - - * - - - | - * - - - - - - | <-- AD7
89 -> - - - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - - - | - - - - - - - - | <-- GCLK2
LC66 -> - - - - - - - - - - * | - * - - - - - - | <-- |lpm_add_sub:1461|addcore:adder|result_node3
LC102-> - - - - - - - - - * - | - * - - - - - - | <-- |lpm_add_sub:1461|addcore:adder|result_node6
LC70 -> - - - - - - - - * - - | - * - - - - - - | <-- |lpm_add_sub:1461|addcore:adder|result_node7
LC100-> - - - - - - - - - - * | - * - - - - - - | <-- |lpm_add_sub:1462|addcore:adder|result_node3
LC65 -> - - - - - - - - - * - | - * - - - - - - | <-- |lpm_add_sub:1462|addcore:adder|result_node6
LC68 -> - - - - - - - - * - - | - * - - - - - - | <-- |lpm_add_sub:1462|addcore:adder|result_node7
LC78 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add5
LC71 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add4
LC74 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add2
LC76 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add1
LC77 -> - - - - - - - - * * * | - * - - * - * - | <-- num_add0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------- LC35 AD2_RD
| +--------------- LC40 CE2
| | +------------- LC37 OE2
| | | +----------- LC38 RW2
| | | | +--------- LC36 ~1133~1
| | | | | +------- LC45 ~1255~1
| | | | | | +----- LC46 ~1255~2
| | | | | | | +--- LC47 ~1429~1
| | | | | | | | +- LC34 ~1429~2
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC35 -> * - - - - * * - - | - - * - - - - - | <-- AD2_RD
LC40 -> - * - * * - - - - | - - * - - - - - | <-- CE2
LC38 -> - - - * - - - - - | - - * - - - - - | <-- RW2
LC36 -> - * - * - - - - - | - - * - - - - - | <-- ~1133~1
LC45 -> * - - - - - - - - | - - * - - - - - | <-- ~1255~1
LC46 -> * - - - - - - - - | - - * - - - - - | <-- ~1255~2
Pin
58 -> * - - - * * - * * | * - * * * * * * | <-- ad_num0
57 -> * - - - * * * * - | * - * * * * * * | <-- ad_num1
30 -> * * - * - * - * - | * - * * * * * * | <-- AD1_BUSY
77 -> * * - * - * * * * | * - * * * * * * | <-- delaytime1
81 -> - * - * * - - - - | * - * * - * - * | <-- dp_num
16 -> * * - * - * - * - | * - * * * * * * | <-- EA0
18 -> * * - * - * - * - | * - * * * * * * | <-- EA1
19 -> * * - * - * - * - | * - * * * * * * | <-- EA2
83 -> - * - * * * * * * | * - * * - * * * | <-- EA6
85 -> * - - - * * * * * | * - * * * * * * | <-- EA7
86 -> - * - * * * * * * | * - * * - * * * | <-- EA8
87 -> * - - - * * * * * | * - * * * * * * | <-- EA9
94 -> - * - * * * * * * | * - * * - * * * | <-- EA10
89 -> - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * * - * - - - - - | * - * * * * * * | <-- wr_en1
LC72 -> - - - - - - - * * | - - * - * - - - | <-- AD3_RD
LC81 -> * * - * - - * - * | * - * * * * * * | <-- EA3
LC105-> * * - * - * * * * | * - * * * * * * | <-- EA4
LC118-> * - - - * - * - * | * - * * * * * * | <-- EA5
LC73 -> * - - - * * - * - | * - * * * * * * | <-- EA11
LC69 -> * * - * - * - * - | * - * * * * * * | <-- EA12
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
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