#define A_SMB_PEC_1                 0x0010060078#define A_SMB_0                     0x0010060000#define A_SMB_1                     0x0010060008#define SMB_REGISTER_SPACING        0x8#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)#define A_SMB_REGISTER(idx,reg)     (A_SMB_BASE(idx)+(reg))#define R_SMB_XTRA                  0x0000000000#define R_SMB_FREQ                  0x0000000010#define R_SMB_STATUS                0x0000000020#define R_SMB_CMD                   0x0000000030#define R_SMB_START                 0x0000000040#define R_SMB_DATA                  0x0000000050#define R_SMB_CONTROL               0x0000000060#define R_SMB_PEC                   0x0000000070/*  *********************************************************************     * Timer Registers    ********************************************************************* *//* * Watchdog timers */#define A_SCD_WDOG_0		    0x0010020050#define A_SCD_WDOG_1                0x0010020150#define SCD_WDOG_SPACING            0x100#define SCD_NUM_WDOGS		    2#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))#define A_SCD_WDOG_REGISTER(w,r)    (A_SCD_WDOG_BASE(w) + (r))#define R_SCD_WDOG_INIT		    0x0000000000#define R_SCD_WDOG_CNT		    0x0000000008#define R_SCD_WDOG_CFG		    0x0000000010#define A_SCD_WDOG_INIT_0           0x0010020050#define A_SCD_WDOG_CNT_0            0x0010020058#define A_SCD_WDOG_CFG_0            0x0010020060#define A_SCD_WDOG_INIT_1           0x0010020150#define A_SCD_WDOG_CNT_1            0x0010020158#define A_SCD_WDOG_CFG_1            0x0010020160/* * Generic timers */#define A_SCD_TIMER_0		    0x0010020070#define A_SCD_TIMER_1               0x0010020078#define A_SCD_TIMER_2		    0x0010020170#define A_SCD_TIMER_3               0x0010020178#define SCD_NUM_TIMERS		    4#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))#define A_SCD_TIMER_REGISTER(w,r)   (A_SCD_TIMER_BASE(w) + (r))#define R_SCD_TIMER_INIT	    0x0000000000#define R_SCD_TIMER_CNT		    0x0000000010#define R_SCD_TIMER_CFG		    0x0000000020#define A_SCD_TIMER_INIT_0          0x0010020070#define A_SCD_TIMER_CNT_0           0x0010020080#define A_SCD_TIMER_CFG_0           0x0010020090#define A_SCD_TIMER_INIT_1          0x0010020078#define A_SCD_TIMER_CNT_1           0x0010020088#define A_SCD_TIMER_CFG_1           0x0010020098#define A_SCD_TIMER_INIT_2          0x0010020170#define A_SCD_TIMER_CNT_2           0x0010020180#define A_SCD_TIMER_CFG_2           0x0010020190#define A_SCD_TIMER_INIT_3          0x0010020178#define A_SCD_TIMER_CNT_3           0x0010020188#define A_SCD_TIMER_CFG_3           0x0010020198#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define A_SCD_SCRATCH		   0x0010020C10#define A_SCD_ZBBUS_CYCLE_COUNT	   0x0010030000#define A_SCD_ZBBUS_CYCLE_CP0	   0x0010020C00#define A_SCD_ZBBUS_CYCLE_CP1	   0x0010020C08#endif /* 1250 PASS2 || 112x PASS1 *//*  *********************************************************************     * System Control Registers    ********************************************************************* */#define A_SCD_SYSTEM_REVISION       0x0010020000#define A_SCD_SYSTEM_CFG            0x0010020008#define A_SCD_SYSTEM_MANUF          0x0010038000/*  *********************************************************************     * System Address Trap Registers    ********************************************************************* */#define A_ADDR_TRAP_INDEX           0x00100200B0#define A_ADDR_TRAP_REG             0x00100200B8#define A_ADDR_TRAP_UP_0            0x0010020400#define A_ADDR_TRAP_UP_1            0x0010020408#define A_ADDR_TRAP_UP_2            0x0010020410#define A_ADDR_TRAP_UP_3            0x0010020418#define A_ADDR_TRAP_DOWN_0          0x0010020420#define A_ADDR_TRAP_DOWN_1          0x0010020428#define A_ADDR_TRAP_DOWN_2          0x0010020430#define A_ADDR_TRAP_DOWN_3          0x0010020438#define A_ADDR_TRAP_CFG_0           0x0010020440#define A_ADDR_TRAP_CFG_1           0x0010020448#define A_ADDR_TRAP_CFG_2           0x0010020450#define A_ADDR_TRAP_CFG_3           0x0010020458#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define A_ADDR_TRAP_REG_DEBUG	    0x0010020460#endif /* 1250 PASS2 || 112x PASS1 *//*  *********************************************************************     * System Interrupt Mapper Registers    ********************************************************************* */#define A_IMR_CPU0_BASE                 0x0010020000#define A_IMR_CPU1_BASE                 0x0010022000#define IMR_REGISTER_SPACING            0x2000#define IMR_REGISTER_SPACING_SHIFT      13#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))#define R_IMR_INTERRUPT_DIAG            0x0010#define R_IMR_INTERRUPT_MASK            0x0028#define R_IMR_INTERRUPT_TRACE           0x0038#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040#define R_IMR_LDT_INTERRUPT_SET         0x0048#define R_IMR_LDT_INTERRUPT             0x0018#define R_IMR_LDT_INTERRUPT_CLR         0x0020#define R_IMR_MAILBOX_CPU               0x00c0#define R_IMR_ALIAS_MAILBOX_CPU         0x1000#define R_IMR_MAILBOX_SET_CPU           0x00C8#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008#define R_IMR_MAILBOX_CLR_CPU           0x00D0#define R_IMR_INTERRUPT_STATUS_BASE     0x0100#define R_IMR_INTERRUPT_STATUS_COUNT    7#define R_IMR_INTERRUPT_MAP_BASE        0x0200#define R_IMR_INTERRUPT_MAP_COUNT       64/*  *********************************************************************     * System Performance Counter Registers    ********************************************************************* */#define A_SCD_PERF_CNT_CFG          0x00100204C0#define A_SCD_PERF_CNT_0            0x00100204D0#define A_SCD_PERF_CNT_1            0x00100204D8#define A_SCD_PERF_CNT_2            0x00100204E0#define A_SCD_PERF_CNT_3            0x00100204E8/*  *********************************************************************     * System Bus Watcher Registers    ********************************************************************* */#define A_SCD_BUS_ERR_STATUS        0x0010020880#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0#endif /* 1250 PASS2 || 112x PASS1 */#define A_BUS_ERR_DATA_0            0x00100208A0#define A_BUS_ERR_DATA_1            0x00100208A8#define A_BUS_ERR_DATA_2            0x00100208B0#define A_BUS_ERR_DATA_3            0x00100208B8#define A_BUS_L2_ERRORS             0x00100208C0#define A_BUS_MEM_IO_ERRORS         0x00100208C8/*  *********************************************************************     * System Debug Controller Registers    ********************************************************************* */#define A_SCD_JTAG_BASE             0x0010000000/*  *********************************************************************     * System Trace Buffer Registers    ********************************************************************* */#define A_SCD_TRACE_CFG             0x0010020A00#define A_SCD_TRACE_READ            0x0010020A08#define A_SCD_TRACE_EVENT_0         0x0010020A20#define A_SCD_TRACE_EVENT_1         0x0010020A28#define A_SCD_TRACE_EVENT_2         0x0010020A30#define A_SCD_TRACE_EVENT_3         0x0010020A38#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58#define A_SCD_TRACE_EVENT_4         0x0010020A60#define A_SCD_TRACE_EVENT_5         0x0010020A68#define A_SCD_TRACE_EVENT_6         0x0010020A70#define A_SCD_TRACE_EVENT_7         0x0010020A78#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98/*  *********************************************************************     * System Generic DMA Registers    ********************************************************************* */#define A_DM_0		  	    0x0010020B00#define A_DM_1		  	    0x0010020B20#define A_DM_2			    0x0010020B40#define A_DM_3			    0x0010020B60#define DM_REGISTER_SPACING	    0x20#define DM_NUM_CHANNELS		    4#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))#define R_DM_DSCR_BASE		    0x0000000000#define R_DM_DSCR_COUNT		    0x0000000008#define R_DM_CUR_DSCR_ADDR	    0x0000000010#define R_DM_DSCR_BASE_DEBUG	    0x0000000018#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define A_DM_PARTIAL_0		    0x0010020ba0#define A_DM_PARTIAL_1		    0x0010020ba8#define A_DM_PARTIAL_2		    0x0010020bb0#define A_DM_PARTIAL_3		    0x0010020bb8#define DM_PARTIAL_REGISTER_SPACING 0x8#define A_DM_PARTIAL(idx)	    (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))#endif /* 1250 PASS3 || 112x PASS1 */#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define A_DM_CRC_0		    0x0010020b80#define A_DM_CRC_1		    0x0010020b90#define DM_CRC_REGISTER_SPACING	    0x10#define DM_CRC_NUM_CHANNELS	    2#define A_DM_CRC_BASE(idx)	    (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))#define A_DM_CRC_REGISTER(idx,reg)  (A_DM_CRC_BASE(idx) + (reg))#define R_CRC_DEF_0		    0x00#define R_CTCP_DEF_0		    0x08#endif /* 1250 PASS3 || 112x PASS1 *//*  *********************************************************************    *  Physical Address Map    ********************************************************************* */#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)#define A_PHYS_GENBUS			_SB_MAKE64(0x0010090000)#define A_PHYS_GENBUS_END		_SB_MAKE64(0x0040000000)#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)#define PHYS_L2CACHE_NUM_WAYS           4#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)#endif