/*  *********************************************************************    *  SB1250 Board Support Package    *      *  Memory Controller constants              File: sb1250_mc.h           *      *  This module contains constants and macros useful for    *  programming the memory controller.    *      *  SB1250 specification level:  User's manual 1/02/02    *      *  Author:  Mitch Lichtenberg    *      *********************************************************************      *    *  Copyright 2000,2001,2002,2003    *  Broadcom Corporation. All rights reserved.    *      *  This program is free software; you can redistribute it and/or     *  modify it under the terms of the GNU General Public License as     *  published by the Free Software Foundation; either version 2 of     *  the License, or (at your option) any later version.    *    *  This program is distributed in the hope that it will be useful,    *  but WITHOUT ANY WARRANTY; without even the implied warranty of    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    *  GNU General Public License for more details.    *    *  You should have received a copy of the GNU General Public License    *  along with this program; if not, write to the Free Software    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,     *  MA 02111-1307 USA    ********************************************************************* */#ifndef _SB1250_MC_H#define _SB1250_MC_H#include "sb1250_defs.h"/* * Memory Channel Config Register (table 6-14) */#define S_MC_RESERVED0              0#define M_MC_RESERVED0              _SB_MAKEMASK(8,S_MC_RESERVED0)#define S_MC_CHANNEL_SEL            8#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8,S_MC_CHANNEL_SEL)#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL)#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL)#define S_MC_BANK0_MAP              16#define M_MC_BANK0_MAP              _SB_MAKEMASK(4,S_MC_BANK0_MAP)#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK0_MAP)#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP)#define K_MC_BANK0_MAP_DEFAULT      0x00#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)#define S_MC_BANK1_MAP              20#define M_MC_BANK1_MAP              _SB_MAKEMASK(4,S_MC_BANK1_MAP)#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK1_MAP)#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP)#define K_MC_BANK1_MAP_DEFAULT      0x08#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)#define S_MC_BANK2_MAP              24#define M_MC_BANK2_MAP              _SB_MAKEMASK(4,S_MC_BANK2_MAP)#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK2_MAP)#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP)#define K_MC_BANK2_MAP_DEFAULT      0x09#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)#define S_MC_BANK3_MAP              28#define M_MC_BANK3_MAP              _SB_MAKEMASK(4,S_MC_BANK3_MAP)#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK3_MAP)#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP)#define K_MC_BANK3_MAP_DEFAULT      0x0C#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)#define M_MC_RESERVED1              _SB_MAKEMASK(8,32)#define S_MC_QUEUE_SIZE		    40#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4,S_MC_QUEUE_SIZE)#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE)#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE)#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)#define S_MC_AGE_LIMIT              44#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4,S_MC_AGE_LIMIT)#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x,S_MC_AGE_LIMIT)#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT)#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)#define S_MC_WR_LIMIT               48#define M_MC_WR_LIMIT               _SB_MAKEMASK(4,S_MC_WR_LIMIT)#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x,S_MC_WR_LIMIT)#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT)#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)#define M_MC_IOB1HIGHPRIORITY	    _SB_MAKEMASK1(52)#define M_MC_RESERVED2              _SB_MAKEMASK(3,53)#define S_MC_CS_MODE                56#define M_MC_CS_MODE                _SB_MAKEMASK(4,S_MC_CS_MODE)#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x,S_MC_CS_MODE)#define G_MC_CS_MODE(x)             _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE)#define K_MC_CS_MODE_MSB_CS         0#define K_MC_CS_MODE_INTLV_CS       15#define K_MC_CS_MODE_MIXED_CS_10    12#define K_MC_CS_MODE_MIXED_CS_30    6#define K_MC_CS_MODE_MIXED_CS_32    3#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)#define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)#define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)#define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)#define M_MC_DEBUG                  _SB_MAKEMASK1(63)#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \				V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \				V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT/* * Memory clock config register (Table 6-15) * * Note: this field has been updated to be consistent with the errata to 0.2 */#define S_MC_CLK_RATIO              0#define M_MC_CLK_RATIO              _SB_MAKEMASK(4,S_MC_CLK_RATIO)#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x,S_MC_CLK_RATIO)#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO)#define K_MC_CLK_RATIO_2X           4#define K_MC_CLK_RATIO_25X          5#define K_MC_CLK_RATIO_3X           6#define K_MC_CLK_RATIO_35X          7#define K_MC_CLK_RATIO_4X           8#define K_MC_CLK_RATIO_45X	    9#define V_MC_CLK_RATIO_2X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X#define S_MC_REF_RATE                8#define M_MC_REF_RATE                _SB_MAKEMASK(8,S_MC_REF_RATE)#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x,S_MC_REF_RATE)#define G_MC_REF_RATE(x)             _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE)#define K_MC_REF_RATE_100MHz         0x62#define K_MC_REF_RATE_133MHz         0x81#define K_MC_REF_RATE_200MHz         0xC4 #define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz#define S_MC_CLOCK_DRIVE             16#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE)#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE)#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE)#define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)#define S_MC_DATA_DRIVE              20#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4,S_MC_DATA_DRIVE)#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x,S_MC_DATA_DRIVE)#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE)#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)#define S_MC_ADDR_DRIVE              24#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4,S_MC_ADDR_DRIVE)#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE)#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)#endif /* 1250 PASS3 || 112x PASS1 */#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)#define S_MC_DQI_SKEW               32#define M_MC_DQI_SKEW               _SB_MAKEMASK(8,S_MC_DQI_SKEW)#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x,S_MC_DQI_SKEW)#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW)#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)#define S_MC_DQO_SKEW               40#define M_MC_DQO_SKEW               _SB_MAKEMASK(8,S_MC_DQO_SKEW)#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x,S_MC_DQO_SKEW)#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW)#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)#define S_MC_ADDR_SKEW               48#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8,S_MC_ADDR_SKEW)#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x,S_MC_ADDR_SKEW)#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW)#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)#define S_MC_DLL_DEFAULT             56#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8,S_MC_DLL_DEFAULT)#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT)#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT)#define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \                                     V_MC_ADDR_SKEW_DEFAULT | \                                     V_MC_DQO_SKEW_DEFAULT | \                                     V_MC_DQI_SKEW_DEFAULT | \                                     V_MC_ADDR_DRIVE_DEFAULT | \                                     V_MC_DATA_DRIVE_DEFAULT | \                                     V_MC_CLOCK_DRIVE_DEFAULT | \                                     V_MC_REF_RATE_DEFAULT /* * DRAM Command Register (Table 6-13) */#define S_MC_COMMAND                0#define M_MC_COMMAND                _SB_MAKEMASK(4,S_MC_COMMAND)#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x,S_MC_COMMAND)#define G_MC_COMMAND(x)             _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND)#define K_MC_COMMAND_EMRS           0#define K_MC_COMMAND_MRS            1#define K_MC_COMMAND_PRE            2#define K_MC_COMMAND_AR             3#define K_MC_COMMAND_SETRFSH        4#define K_MC_COMMAND_CLRRFSH        5#define K_MC_COMMAND_SETPWRDN       6#define K_MC_COMMAND_CLRPWRDN       7#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)#define M_MC_CS0                    _SB_MAKEMASK1(4)#define M_MC_CS1                    _SB_MAKEMASK1(5)#define M_MC_CS2                    _SB_MAKEMASK1(6)#define M_MC_CS3                    _SB_MAKEMASK1(7)/* * DRAM Mode Register (Table 6-14) */#define S_MC_EMODE                  0#define M_MC_EMODE                  _SB_MAKEMASK(15,S_MC_EMODE)#define V_MC_EMODE(x)               _SB_MAKEVALUE(x,S_MC_EMODE)#define G_MC_EMODE(x)               _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE)#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)