#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)#define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)#define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)#define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)#define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)#define V_MAC_IFG_THRSH_10     V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)#define V_MAC_IFG_THRSH_100    V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)#define V_MAC_IFG_THRSH_1000   V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)#define V_MAC_SLOT_SIZE_10     V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)#define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)#define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)#define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)#define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)#define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)#define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)/* * MAC VLAN Tag Registers (Table 9-16) * Register: MAC_VLANTAG_0 * Register: MAC_VLANTAG_1 * Register: MAC_VLANTAG_2 */#define S_MAC_VLAN_TAG           _SB_MAKE64(0)#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32,S_MAC_VLAN_TAG)#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET)#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET)#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET)#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)#endif /* 1250 PASS3 || 112x PASS1 *//* * MAC Status Registers (Table 9-17) * Also used for the MAC Interrupt Mask Register (Table 9-18) * Register: MAC_STATUS_0 * Register: MAC_STATUS_1 * Register: MAC_STATUS_2 * Register: MAC_INT_MASK_0 * Register: MAC_INT_MASK_1 * Register: MAC_INT_MASK_2 *//*  * Use these constants to shift the appropriate channel * into the CH0 position so the same tests can be used * on each channel. */#define S_MAC_RX_CH0                _SB_MAKE64(0)#define S_MAC_RX_CH1                _SB_MAKE64(8)#define S_MAC_TX_CH0                _SB_MAKE64(16)#define S_MAC_TX_CH1                _SB_MAKE64(24)#define S_MAC_TXCHANNELS	    _SB_MAKE64(16)	/* this is 1st TX chan */#define S_MAC_CHANWIDTH             _SB_MAKE64(8)	/* bits between channels *//* *  These are the same as RX channel 0.  The idea here *  is that you'll use one of the "S_" things above *  and pass just the six bits to a DMA-channel-specific ISR */#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8,0)#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)	/* only for TX channels */#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)	/* only for RX channels *//* * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see * also DMA_TX/DMA_RX in sb_regs.h). */#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)#define M_MAC_STATUS_CHANNEL(ch,txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_EOP_SEEN(ch,txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_HWM(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_LWM(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_DSCR(ch,txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_ERR(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_DZERO(ch,txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_DROP(ch,txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx))#define M_MAC_STATUS_OTHER_ERR          _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40)#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_MAC_SPLIT_EN		    _SB_MAKEMASK1(47) 	/* interrupt mask only */#endif /* 1250 PASS2 || 112x PASS1 */#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_MAC_TX_PAUSE_ON	    _SB_MAKEMASK1(52)#endif /* 1250 PASS3 || 112x PASS1 *//* * MAC Fifo Pointer Registers (Table 9-19)    [Debug register] * Register: MAC_FIFO_PTRS_0 * Register: MAC_FIFO_PTRS_1 * Register: MAC_FIFO_PTRS_2 */#define S_MAC_TX_WRPTR              _SB_MAKE64(0)#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6,S_MAC_TX_WRPTR)#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x,S_MAC_TX_WRPTR)#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR)#define S_MAC_TX_RDPTR              _SB_MAKE64(8)#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6,S_MAC_TX_RDPTR)#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x,S_MAC_TX_RDPTR)#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR)#define S_MAC_RX_WRPTR              _SB_MAKE64(16)#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6,S_MAC_RX_WRPTR)#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x,S_MAC_RX_WRPTR)#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR)#define S_MAC_RX_RDPTR              _SB_MAKE64(24)#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6,S_MAC_RX_RDPTR)#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x,S_MAC_RX_RDPTR)#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR)/* * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register] * Register: MAC_EOPCNT_0 * Register: MAC_EOPCNT_1 * Register: MAC_EOPCNT_2 */#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER)#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER)#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER)#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER)#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER)#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER)/* * MAC Recieve Address Filter Exact Match Registers (Table 9-21) * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 *//* No bitfields *//* * MAC Receive Address Filter Mask Registers * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 *//* No bitfields *//* * MAC Recieve Address Filter Hash Match Registers (Table 9-22) * Registers: MAC_HASH0_0 through MAC_HASH7_0 * Registers: MAC_HASH0_1 through MAC_HASH7_1 * Registers: MAC_HASH0_2 through MAC_HASH7_2 *//* No bitfields *//* * MAC Transmit Source Address Registers (Table 9-23) * Register: MAC_ETHERNET_ADDR_0 * Register: MAC_ETHERNET_ADDR_1 * Register: MAC_ETHERNET_ADDR_2 *//* No bitfields *//* * MAC Packet Type Configuration Register * Register: MAC_TYPE_CFG_0 * Register: MAC_TYPE_CFG_1 * Register: MAC_TYPE_CFG_2 */#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)#define S_TYPECFG_TYPE0		_SB_MAKE64(0)#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16,S_TYPECFG_TYPE0)#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE0)#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0)#define S_TYPECFG_TYPE1		_SB_MAKE64(0)#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16,S_TYPECFG_TYPE1)#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE1)#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1)#define S_TYPECFG_TYPE2		_SB_MAKE64(0)#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16,S_TYPECFG_TYPE2)#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE2)#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2)#define S_TYPECFG_TYPE3		_SB_MAKE64(0)#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16,S_TYPECFG_TYPE3)#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE3)#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3)/* * MAC Receive Address Filter Control Registers (Table 9-24) * Register: MAC_ADFILTER_CFG_0 * Register: MAC_ADFILTER_CFG_1 * Register: MAC_ADFILTER_CFG_2 */#define M_MAC_ALLPKT_EN	        _SB_MAKEMASK1(0)#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_MAC_ALLMCAST_EN	_SB_MAKEMASK1(7)#endif /* 1250 PASS2 || 112x PASS1 */#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)#define V_MAC_IPHDR_OFFSET(x)	_SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)#define G_MAC_IPHDR_OFFSET(x)	_SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)#define V_MAC_RX_CRC_OFFSET(x)	_SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)#define G_MAC_RX_CRC_OFFSET(x)	_SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET)#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET)#define V_MAC_RX_PKT_OFFSET(x)	_SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET)#define G_MAC_RX_PKT_OFFSET(x)	_SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET)#define M_MAC_FWDPAUSE_EN	_SB_MAKEMASK1(32)#define M_MAC_VLAN_DET_EN	_SB_MAKEMASK1(33)#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)#define V_MAC_RX_CH_MSN_SEL(x)	_SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)#define G_MAC_RX_CH_MSN_SEL(x)	_SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)#endif /* 1250 PASS3 || 112x PASS1 *//* * MAC Receive Channel Select Registers (Table 9-25) *//* no bitfields *//* * MAC MII Management Interface Registers (Table 9-26) * Register: MAC_MDIO_0 * Register: MAC_MDIO_1 * Register: MAC_MDIO_2 */#define S_MAC_MDC		0#define S_MAC_MDIO_DIR		1#define S_MAC_MDIO_OUT		2#define S_MAC_GENC		3#define S_MAC_MDIO_IN		4#define M_MAC_MDC		_SB_MAKEMASK1(S_MAC_MDC)#define M_MAC_MDIO_DIR		_SB_MAKEMASK1(S_MAC_MDIO_DIR)#define M_MAC_MDIO_DIR_INPUT	_SB_MAKEMASK1(S_MAC_MDIO_DIR)#define M_MAC_MDIO_OUT		_SB_MAKEMASK1(S_MAC_MDIO_OUT)#define M_MAC_GENC		_SB_MAKEMASK1(S_MAC_GENC)#define M_MAC_MDIO_IN		_SB_MAKEMASK1(S_MAC_MDIO_IN)#endif